This presentation reviews the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools down to 14 nm node, as well as the factors that ultimately limit the predictability of such models. It also outlines the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.