Overlay variations between different layers in Integrated Circuits fabrication can result in poor circuit performance, even worst it can cause circuit mal function and consequently affect process yield. Coupled with other lithographic process variations this effect can be highly magnified. This leads to the fact that searching for interconnects hot spots should include overlay variations into account. The accuracy of inclusion of the overlay variation effect comes at the expense of a more complex simulation setup. Many issues should be taken into consideration including runtime, process combinations to be considered and the feasibility of providing a hint function for correction.
In this paper we present a systematic approach for classification of interconnects durability through the lithographic process, taking into account focus, dose and overlay variations, the approach also provides information about the cause for the low durability that can be useful for building a more robust design.
This classification can be accessible at the layout design level. With this information in hand, designers can test the layout while building up their circuit. Modifications to the layout for higher interconnects durability can be easily made. These modifications would be extremely expensive if they had to be made after design house tape out.
We verify this method by showing real wafer failures, due to bad interconnect design, against interconnects' durability classifications from our method.