Advanced Mask Process Modeling for 45-nm and 32-nm Nodes

ABSTRACT

As tolerance requirements for the lithography process continue to shrink with each new technology node, the contributions of all process sequence steps to the critical dimension error budgets are being closely examined, including wafer exposure, resist processing, pattern etch, as well as the photomask process employed during the wafer exposure. Along with efforts to improve the mask manufacturing processes, the elimination of residual mask errors via pattern correction has gained renewed attention. The portfolio of correction tools for mask process effects is derived from well established techniques commonly used in optical proximity correction and in electron beam proximity effect compensation. The process component that is not well captured in the correction methods deployed in mask manufacturing today is etch. A mask process model to describe the process behavior and to capture the physical effects leading to deviation of the critical dimension from the target value represents the key component of model-based correction and verification. This paper presents the flow for generating mask process models that describe both short-range and long-range mask process effects, including proximity loading effects from etching, pattern density loading effects, and across-mask process non-uniformity. The flow is illustrated with measurement data from real test masks. Application of models for both mask process correction and verification is discussed.