White Papers
A GDS-based Mask Data Preparation Flow - Data Volume Containment by Hierarchical Data Processing
As the industry enters the development of the 65nm node the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which turns what used to be the relatively simple task of mask data preparation into a real bottleneck. This discussion introduces the data preparation scheme in the mask house and analyzes its evolution. Mask data preparation (MDP) has evolved from a flow that only needed to support a single mask lithography tool data format (MEBESâ„¢) with minimal data alteration steps to one which requires the support of many mask lithography tool data formats and at the same time requires significant data alteration to support the increased precision necessary for today's advanced masks.. However, the MDP flow developed around the MEBESâ„¢ format and it's derivatives still exists. The design community has migrated towards the use of hierarchical data formats and processes to control file size and processing time. MDP, which from a file size and process complexity point of view is beginning to look more and more like the advanced RET operations performed on the data prior to mask manufacturing, is still standardized on a flat data format that is poorly optimized for a growing number of mask lithography tools. Based on examples it will be shown how this complicates the data handling further. An alternate data preparation flow accommodating the larger files and re-gaining flexibility for turnaround time (TAT) and throughput management is suggested. This flow utilizes the hierarchical GDS-II format as the exchange format for mask data preparation. It complements the existing flow for the most complex designs. The introduction of a hierarchical exchange format enables the transfer of a number of necessary data preparation steps into the hierarchical domain. Data processing strategies are discussed. The paper illustrates the benefit of hierarchical processing based on GDS-II files with experimental data on file size reduction and TAT improvement for direct format conversions vs. re-fracturing as well as other processing steps. The implications for the established data preparation approaches and potential alternatives for the communication between the mask manufacturer and the customer will be discussed. The potential for further enhancements by converting to a hierarchical format that has a more efficient data representation than the commonly used GDS-II format will be discussed and illustrated.
More White Papers
Assessment and comparison of different approaches for mask write time reduction
The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout, how they influence shot count as the main driver for mask writing time and techniques to reduce that impact. The paper discusses the application of resolution enhancements and layout simplification techniques; the fracture step and optimization methods; mask writing and novel ideas for shot count reduction. The paper will describe and compare the following techniques: optimized fracture, pre-fracture jog alignment, generalization of shot definition (L-shot), multi-resolution writing, optimized-based fracture, and optimized OPC output. The comparison of shot count reduction techniques will consider the impact of changes to the current state of the art using the following criteria: computational effort, CD control on the mask, mask rule compliance for manufacturing and inspection, and the software and hardware changes required to achieve the mask write time reduction. The paper will introduce the concepts and present some data preparation results based on process correction and fracturing tools.
Contour-Based Self-Aligning Calibration of OPC Models
SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy for 1D features. As the method progresses, there are emerging challenges that are normally not found in CD based calibration. One such challenge is the need to align SEM contours with calibration features. This is particularly important in determining model accuracy since contour calibration typically involves a cost function that compares the SEM contours to the simulated print images.
This work explores a technique to include contour alignment errors into the calibration cost function. For each contour and its corresponding simulated print, the cost function returns an error value for a given set of model parameters. The error represents how well the model simulation compared to input contour. In addition, it also contains information on how far or how close the contour is aligned to simulation. Misalignment is to be eliminated on the fly during calibration and to be reported at the end of calibration.
In this paper we describe the proposed technique and compare the results of calibration between aligned and misaligned contour data.
Device Performances Analysis of Standard-Cells Transistors using Silicon Simulation and Build-in Device Simulation
A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13µm Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.
Improved Process Window Modeling Techniques
The continuous reduction of device dimensions and densities of integrated circuits increases the demand for accurate process window models used in optical proximity correction. Beam focus and dose are process parameters that have significant contribution to the overall critical feature dimension error budget. The increased number of process conditions adds to the model calibration time since a new optical model needs to be generated for each focus condition. This study shows how several techniques can reduce the calibration time by appropriate selection of process conditions and features while maintaining good accuracy. Experimental data is used to calibrate models using a reduced set of data. The resulting model is compared with the model calibrated using the full set of data. The results show that using a reduced set of process conditions and using process sensitive features can yield a model as accurate as the model calibrated using the full set but in a shorter amount of time.
An Optimized OPC and MDP Flow for Reducing Mask Write Time and Mask Cost
During optical proximity correction (OPC), layout edges or fragments are migrated to proper positions in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE are a part of the cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window, catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology nodes becomes finer, there are conflicts between OPC accuracy and stability, especially for metal layers. To address this, several techniques have been introduced, including target smoothing, process window-aware OPC, model-based re-targeting, and adaptive OPC. Those techniques invoke additional edges, or fragments, prior to correction or during OPC iteration. As a result, the number of jogs – and shot count – are dramatically increased. There is trade-off relationship between data complexity and various methods for OPC stability. In this paper, those relationships have been investigated. Mask shot count reduction is achieved by reducing the number of jogs with jog smoothing. The effect of jog smoothing on OPC output – in view of OPC performance and mask data preparation - was studied quantitatively for respective technology nodes.
Generalization of Shot Definition for Variable Shaped E-Beam Machines for Write Time Reduction
By adding a second deflector-aperture stage to the electron beam column of a vector shaped mask writer in which the aperture has the shape of a cross, one gains the ability to print a parameterized “L-shaped” exposure. This is the most modest generalization of the shot shape in such machines that retains the current paradigm of exposing a non-overlapping cover of parameterized prototypical shapes. These “L” shapes occur frequently in such covers and each one patterns the equivalent of two adjacent rectangular shots. While this proposal does require hardware changes, we suggest that the substantial potential gain combined with the localized nature of the disturbance to present manufacturing pipelines justifies consideration of the technique. In this paper we concentrate on the implications to and initial results for mask data preparation (MDP) for L-shots.
NP-Completeness Result for Positive Line-By-Fill SADP Process
Double patterning (DP) is a necessity for at and below 32nm half pitch production. The two top contending DP technologies are litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP). While both LELE and SADP are actively researched and optimized on the process side [1] [2] [3] [4], CAD support for them has been very different. When cut candidates can be explicitly specified, the problem of LELE mask assignment transforms into the familiar 2-colorability problem and benefits from the extensive research ranging from what originally was conducted for alt-PSM lithography [5], to more recently proposed new techniques for LELE [6], and proof of the inherent computational limitation imposed by hierarchy [7].CAD support for SADP, on the other hand, is almost non-existent. Such lack of CAD support for SADP is not coincidental. For a layout, LELE solutions tend to look similar while SADP solutions can be vastly different in style. Due to the flexibility offered by trim mask, SADP inherently has a much larger solution space than LELE. In this paper, we take the first step in investigating the CAD implications of the positive line-by-fill SADP process by proving that the problem of SADP manufacturability is NP-complete.
OPC Recipe Optimization Using Simulated Annealing
One of the major problems in the RET flow is OPC recipe creation. The existence of numerous parameters to tune and the interdependence between them complicates the process of recipe optimization and makes it very tedious. There is usually no standard methodology to choose the initial values for the recipe settings or to determine stable regions of operation. In fact, parameters are usually optimized independently or chosen to resolve a certain issue for a specific design without quantifying its effect on the quality of the recipe or how it might affect other designs. Another problem arises when a quick fix is needed for an old recipe to build new design masks, and this causes the stacking of many customization statements in the OPC recipe, which in turns increases its complexity. Consequently, the experience of the developer is highly required to build a good as well as a stable recipe. In this context, simulated annealing is proposed to optimize OPC recipes. It will be shown how many parameters can be optimized simultaneously and how we can get insight about the stability of the recipe.
Optimize the OPC Control Recipe With Cost Function
With rapidly shrinking feature sizes, full chip robust Optical Proximity Correction (OPC) will take longer due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more difficult. The critical dimension of the design features is smaller than the exposure wavelength, and there is only limited room for the OPC correction. Usually very complicated scripts need to be developed to handle the shrinking designs. So when you are defining a parameter value in your OPC control recipe, one problem is how to find the optimum setting. Usually there are many parameters in the script, some of which may have impact on others' performance. We demonstrate an approach to optimizing the critical parameters settings with cost functions to reduce the difficulty of OPC recipe development.