White Papers
Automatic Assist Feature Placement Optimization Based on Process-Variability Reduction
To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window. With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such as image contrast and other edge- and image-based objective functions. In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations assess the allowed exposure range that prevents scatter bars from printing on the wafer.
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Challenges for Patterning Process Models Applied to Large Scale
Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist and etch process models. This paper will review the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools, as well as the factors that ultimately limit the predictability of such models. In addition, this paper will outline the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.
Patterning Process Models Presentation
This presentation reviews the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools down to 14 nm node, as well as the factors that ultimately limit the predictability of such models. It also outlines the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.
Contour-Based Self-Aligning Calibration of OPC Models
SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy for 1D features. As the method progresses, there are emerging challenges that are normally not found in CD based calibration. One such challenge is the need to align SEM contours with calibration features. This is particularly important in determining model accuracy since contour calibration typically involves a cost function that compares the SEM contours to the simulated print images.
This work explores a technique to include contour alignment errors into the calibration cost function. For each contour and its corresponding simulated print, the cost function returns an error value for a given set of model parameters. The error represents how well the model simulation compared to input contour. In addition, it also contains information on how far or how close the contour is aligned to simulation. Misalignment is to be eliminated on the fly during calibration and to be reported at the end of calibration.
In this paper we describe the proposed technique and compare the results of calibration between aligned and misaligned contour data.
Device Performances Analysis of Standard-Cells Transistors using Silicon Simulation and Build-in Device Simulation
A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13µm Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.
Improved Process Window Modeling Techniques
The continuous reduction of device dimensions and densities of integrated circuits increases the demand for accurate process window models used in optical proximity correction. Beam focus and dose are process parameters that have significant contribution to the overall critical feature dimension error budget. The increased number of process conditions adds to the model calibration time since a new optical model needs to be generated for each focus condition. This study shows how several techniques can reduce the calibration time by appropriate selection of process conditions and features while maintaining good accuracy. Experimental data is used to calibrate models using a reduced set of data. The resulting model is compared with the model calibrated using the full set of data. The results show that using a reduced set of process conditions and using process sensitive features can yield a model as accurate as the model calibrated using the full set but in a shorter amount of time.
An Optimized OPC and MDP Flow for Reducing Mask Write Time and Mask Cost
During optical proximity correction (OPC), layout edges or fragments are migrated to proper positions in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE are a part of the cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window, catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology nodes becomes finer, there are conflicts between OPC accuracy and stability, especially for metal layers. To address this, several techniques have been introduced, including target smoothing, process window-aware OPC, model-based re-targeting, and adaptive OPC. Those techniques invoke additional edges, or fragments, prior to correction or during OPC iteration. As a result, the number of jogs – and shot count – are dramatically increased. There is trade-off relationship between data complexity and various methods for OPC stability. In this paper, those relationships have been investigated. Mask shot count reduction is achieved by reducing the number of jogs with jog smoothing. The effect of jog smoothing on OPC output – in view of OPC performance and mask data preparation - was studied quantitatively for respective technology nodes.
Generalization of Shot Definition for Variable Shaped E-Beam Machines for Write Time Reduction
By adding a second deflector-aperture stage to the electron beam column of a vector shaped mask writer in which the aperture has the shape of a cross, one gains the ability to print a parameterized “L-shaped” exposure. This is the most modest generalization of the shot shape in such machines that retains the current paradigm of exposing a non-overlapping cover of parameterized prototypical shapes. These “L” shapes occur frequently in such covers and each one patterns the equivalent of two adjacent rectangular shots. While this proposal does require hardware changes, we suggest that the substantial potential gain combined with the localized nature of the disturbance to present manufacturing pipelines justifies consideration of the technique. In this paper we concentrate on the implications to and initial results for mask data preparation (MDP) for L-shots.
Model-Based Double-Dipole Lithography for Sub-30-nm Node Device
As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL requirements have been also emerged to improve the process margin and to reduce the mask-enhanced error factor (MEEF), which is to maximize the resolution and image contrast. There are two approaches in DDL i.e. model based and rule based-DDLs. Rule-based DDL, in which the patterns are decomposed by the simple rules such as x- and y- directional rules, shows the low process margin in the 2-dimension (2D) patterns, i.e., line-end to line-end, line-end to bar and semi-isolated bars. In this paper, we first present various analyses of our new model-based DDL (MBDDL) method. Our goal is to maximize the process margin of the 2D patterns.
NP-Completeness Result for Positive Line-By-Fill SADP Process
Double patterning (DP) is a necessity for at and below 32nm half pitch production. The two top contending DP technologies are litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP). While both LELE and SADP are actively researched and optimized on the process side [1] [2] [3] [4], CAD support for them has been very different. When cut candidates can be explicitly specified, the problem of LELE mask assignment transforms into the familiar 2-colorability problem and benefits from the extensive research ranging from what originally was conducted for alt-PSM lithography [5], to more recently proposed new techniques for LELE [6], and proof of the inherent computational limitation imposed by hierarchy [7].CAD support for SADP, on the other hand, is almost non-existent. Such lack of CAD support for SADP is not coincidental. For a layout, LELE solutions tend to look similar while SADP solutions can be vastly different in style. Due to the flexibility offered by trim mask, SADP inherently has a much larger solution space than LELE. In this paper, we take the first step in investigating the CAD implications of the positive line-by-fill SADP process by proving that the problem of SADP manufacturability is NP-complete.