Technical Papers

This paper investigates contact layer mask planning for DPT, and presents results on two new problems due to hierarchical processing.

LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization when design is not manufacturable with DPT and mask assignment either when it is or despite it is not. Concurrent with the advancements in double patterning process, there has been active research [1] [2] [3] [4] addressing the problem of mask planning. As geometries across the chip can potentially involve in the same conflict, DPT decomposition has been recognized as unbounded [5] [4]. We will show in this paper that the unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of fully flattened design are even more amenable in that they are already positioned with respect to the flat view, and tiles overlap only marginally when they do. While there have been ample research literature in the mask assignment problem with respect to geometries within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special handling needed for peculiar complexities arising from the presence of hierarchy [5] [6]. Hierarchy adds a subtle but significant dimension to the mask planning problems.

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important mask writing time due to the shotcount 4. In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited. Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of DOF and Runtime performance for hole patterning.

With the design rule shrinks rapidly, full chip robust Optical Proximity Correction (OPC) will definitely need longer time due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more difficult. For, the critical dimension of the design features is deeply sub exposure wavelength, and there is only limited room for the OPC correction. Usually very complicated fragment commands need to be developed to handle the shrinking designs, which can be infinitely complicated. So when you finished debug a sophisticated fragment scripts, you still cannot promise that the script is universal for all kinds of design. And when you find some hot spot after you apply OPC correction for certain design, the only thing you can do is to modify your fragmentation script and try to re-apply OPC on this design. But considering the increasing time that is needed for applying full chip OPC nowadays, re-apply OPC will definitely prolong the tape-out time. We here demonstrate an approach of adaptive OPC, with which automatic fragmentation adjustment can be realized. And this will be helpful to reduce the difficulty for OPC recipe development.

A litho hotspot repair hints requires the specifications of how layout edges should be modified. Identifying how layout edges not directly touching the hotspot region is challenging to encode in a rule set. We propose an approach using models called Partition Response Surface Models (pRSM) to estimate the contours changes due to design layout modifications. In this paper we present details of litho hotspot repair hint engine which uses the pRSM models to compute the shape changes amount to resolve a litho hotspot and which can accept constraints from both design considerations or design rule considerations.

Computing repair hints for litho hotspots is made more effective with a model of how Process Window contour bands changes as a function of design layout changes. We have developed a modeling methodology called pRSM (Partition Response Surface Model). In our approach, we create a family of models along with error bound estimate models. We first classify design layout configurations into a small number of partition categories and then build a RSM model and error bound model for each partition category. In this paper we describe our pRSM methodology and present results illustrating the advantages of our methodology over that of traditional RSM approaches.

Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and is intended for use with various Design for Manufacturing applications, such as SmartFill optimizations, accurate parasitic extractions, and depth-of-focus variability compensations. CMP Optimize is tightly integrated with Mentor Graphics’ Calibre product line, which provides planarity hotspot detection, as well as thickness analysis and optimization. CMP Optimize is currently the only solution in the industry that gives designers the ability to build models for copper metallization processes. Much like models for lithography, the customer’s process or foundry team builds and owns the copper models. This white paper introduces the CMP Optimize tool from a model-building perspective. It discusses the necessary inputs, model-building methodology from a calibration and optimization standpoint, output data analysis, and model validation capabilities.