White Papers
Optimization of OPC Runtime Using Efficient Optical Simulation
Model-Based Optical Proximity Correction (MBOPC) is now found in nearly all resolution enhancement recipes used in leading technology integrated circuit fabrication facilities. Many masks now have critical dimensions less than the exposure wavelength, which results in light diffraction that distorts the image projected onto the wafer. The industry is relying more and more on MBOPC to compensate for optical effects that are induced during the exposure of these masks. The MBOPC operation is usually the highest computational time contributor in the RET flow. MBOPC procedures include the fragmentation of layout edges longer than a specific value into a number of subedges(fragments).
The software engine can move and manipulate each fragment to improve the image transferred to the wafer. In the sparse MBOPC approach, each fragment receives one or more optical simulation sites, which is a one-dimensional array of points where light intensity is sampled and calculated. To correctly capture the resist behavior at each simulation site, there must be enough points to ensure extension of the site to a certain distance from the fragment. Adding more points beyond this distance does not add any benefit, but can significantly increase the runtime.
This paper presents an automated method that analyzes layouts for different technology nodes that depend on sparse simulations as their MBOPC engine, and reports the optimized number of simulation points that need to be in the
simulation site to get the desired accuracy and optimum runtime performance.
More White Papers
Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?
Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern with ever smaller dimension in ArF lithography using a fixed exposure wave length of 193nm and prevent printing wafer patterns identical to the shapes drawn on the exposure mask. Resolution enhancement techniques such as Optical Proximity Correction (OPC) enable new technologies to be realized in wafer manufacturing. Sub-resolution assist features (SRAF), or scatter bars (SB), provide critical process window enhancements in the lithography process. Traditionally, SRAF generation is based on geometric rules, which are extracted from a large amount of simulation and empirical wafer data from printing test masks.
A Hybrid model/pattern based OPC approach for improved consistency and TAT
As the technology advances, OPC run time turns to be a big concern and a great deal of our efforts is directed towards speeding up the LITHO operations. In addition, the OPC simulation consistency is sometimes deteriorated which is a critical issue especially for anchor features. On the other hand, full chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC recipes, which is evident for instance for memory design and processor chips. The model based OPC technique is not necessary for such designs provided that the equivalent mask shapes for one cell of these arrays are already known. In this work, we introduce a combined approach using model and pattern based OPC. Pattern matching is used to extract regions from full chips that match the basic designs stored in pre-created libraries. When matching occurs, OPC solution stored in these libraries is used and populated across matched areas. Special treatment for large array boundaries is applied due to proximity effects. Model based OPC is used for the rest of the chip. This approach has two main advantages. First, simulation consistency is greatly improved since the OPC solution for standard cells is priory known. Also, pattern matching is a DRC based tool and thus it is very fast compared to LITHO operations and hence TAT is further enhanced.
Integration of Pattern Matching© into Verification Flows
In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it is much faster than time consuming LITHO operations. Also, its capability to match geometries directly and operability on many layers simultaneously eliminates complex SVRF coding from our flows. Firstly, we will use the pattern matching in order not to run OPC verification on basic designs identified by the OPC engineer to be error free, which is a very useful technique especially in Memory designs and improves the run time. Then, it will be used to detect waivers, which is hard to code, while running verification flows and eliminate it from the output, and consequently the reviewer will not be distracted by it and concentrate on real errors. And finally, it will be used to detect hot spots in a separate very quick run before standard LITHO verification run which gives the designer/OPC engineer the opportunity to fix design/OPC issues without waiting for lengthy verification flows, and that in turns further improves TAT.
Challenges for Patterning Process Models Applied to Large Scale
Full-chip patterning simulation has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasi-rigorous optical models and semi-empirical resist and etch process models. This paper will review the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools, as well as the factors that ultimately limit the predictability of such models. In addition, this paper will outline the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.
Patterning Process Models Presentation
This presentation reviews the steady improvement in the predictive power and runtime performance of the patterning models used in full chip simulation tools down to 14 nm node, as well as the factors that ultimately limit the predictability of such models. It also outlines the new process simulation challenges that emerge as the industry approaches sub-0.25 k1 patterning: improving accuracy and predictability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.
Contour-Based Self-Aligning Calibration of OPC Models
SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy for 1D features. As the method progresses, there are emerging challenges that are normally not found in CD based calibration. One such challenge is the need to align SEM contours with calibration features. This is particularly important in determining model accuracy since contour calibration typically involves a cost function that compares the SEM contours to the simulated print images.
This work explores a technique to include contour alignment errors into the calibration cost function. For each contour and its corresponding simulated print, the cost function returns an error value for a given set of model parameters. The error represents how well the model simulation compared to input contour. In addition, it also contains information on how far or how close the contour is aligned to simulation. Misalignment is to be eliminated on the fly during calibration and to be reported at the end of calibration.
In this paper we describe the proposed technique and compare the results of calibration between aligned and misaligned contour data.
Device Performances Analysis of Standard-Cells Transistors using Silicon Simulation and Build-in Device Simulation
A simple methodology to predict transistors performances due to systematic lithography and etch effects is presented. It is based on physical silicon simulation, followed by device modeling, incorporated in the silicon simulation software. This method enables an easy and efficient analysis of device parameters with the same simulation tool usually used for process analysis. The method is demonstrated on small and large arrays of standard cell blocks, designed for TS013SL (0.13µm Standard Logic for General Purposes) Platform. Electrical parameters, like drive current (Idsat), and Off current (Ioff) were predicted. Comparison between different transistors types, having the same W/L but different layout configuration and various layout environments (around the transistor) was made in terms of performances as well as process variability.
Improved Process Window Modeling Techniques
The continuous reduction of device dimensions and densities of integrated circuits increases the demand for accurate process window models used in optical proximity correction. Beam focus and dose are process parameters that have significant contribution to the overall critical feature dimension error budget. The increased number of process conditions adds to the model calibration time since a new optical model needs to be generated for each focus condition. This study shows how several techniques can reduce the calibration time by appropriate selection of process conditions and features while maintaining good accuracy. Experimental data is used to calibrate models using a reduced set of data. The resulting model is compared with the model calibrated using the full set of data. The results show that using a reduced set of process conditions and using process sensitive features can yield a model as accurate as the model calibrated using the full set but in a shorter amount of time.
An Optimized OPC and MDP Flow for Reducing Mask Write Time and Mask Cost
During optical proximity correction (OPC), layout edges or fragments are migrated to proper positions in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE are a part of the cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window, catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology nodes becomes finer, there are conflicts between OPC accuracy and stability, especially for metal layers. To address this, several techniques have been introduced, including target smoothing, process window-aware OPC, model-based re-targeting, and adaptive OPC. Those techniques invoke additional edges, or fragments, prior to correction or during OPC iteration. As a result, the number of jogs – and shot count – are dramatically increased. There is trade-off relationship between data complexity and various methods for OPC stability. In this paper, those relationships have been investigated. Mask shot count reduction is achieved by reducing the number of jogs with jog smoothing. The effect of jog smoothing on OPC output – in view of OPC performance and mask data preparation - was studied quantitatively for respective technology nodes.