IC Design
Mentor Graphics offers the most comprehensive IC design, verification, DFM and test technologies available today.
Our technologies address the most pressing challenges facing IC development teams for custom analog and digital, digital place and route, mixed-signal and system-on-chip (SoC) designs. Tight collaboration with foundries, IC design houses, systems companies, research and development labs, and industry standards organizations ensures our tools meet state-of-the-art requirements and deliver real competitive value.
IC Design Tools
Digital IC Design
Mentor Graphic's IC implementation system, Olympus-SoC, delivers innovative technologies for fast and high-quality design closure at advanced process nodes.
Analog/Mixed-Signal Verification
Mentor Graphics offers industry leading high-performance simulation and verification solutions for complex analog/mixed-signal System-on-Chip designs.
Calibre Design for Manufacturing
Building on our powerful, production-proven Hyperscaling architecture, Calibre delivers the broadest, most accurate, and best performing DFM solutions in the industry.
Calibre IC Verification & Signoff
Mentor Graphic's IC verification and sign-off includes traditional rule-based physical verification, parasitic extraction, and automated technologies that help improve yield.
Custom IC Design
Mentor Graphics offers integrated solutions for design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout and chip assembly.
Silicon Test and Yield Analysis
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug and yield ramp for today's SoCs. Learn more about Silicon Test and Yield Analysis
White Papers
Modern IC Packaging
Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. View White Paper
Ready for 3D-IC
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon... View White Paper
Upcoming Events
Foundry Partners
Foundry Partners
Mentor Graphics has teamed up with the world's top foundries, including Chartered, Donbgu HiTek, IBM, TSMC, and more, to jointly develop and qualify Calibre DRC, LVS, and PEX rule files.