IC Design

Mentor Graphics offers the most comprehensive IC design, verification, DFM and test technologies available today.

Our technologies address the most pressing challenges facing IC development teams for custom analog and digital, digital place and route, mixed-signal and system-on-chip (SoC) designs. Tight collaboration with foundries, IC design houses, systems companies, research and development labs, and industry standards organizations ensures our tools meet state-of-the-art requirements and deliver real competitive value.

ADMS: Mixed-Signal SoC Design and Verification Workshop

Event: During this lab-intensive technical workshop, you will gain first-hand experience evaluating Questa ADMS, Mentor's Mixed-Signal Simulation Solution. View Event

Introducing Eldo Premier

Increase performance without sacrificing accuracy. Learn more

Pyxis Custom IC Design Platform

Providing dramatic productivity improvements and unique functionality including constraint based custom routing and concurrent editing. Learn more

Introducing Calibre RealTime

On-demand Calibre Signoff Verification in Custom Design Flows. Learn More

Introducing Calibre xACT 3D

High performance extraction engine integrated into design flows reference-level accuracy. Learn More

Introducing Calibre InRoute

Delivering true signoff analysis and automatic DRC/DFM fixes during implementation. Learn More

Introducing Calibre Pattern Matching

Pattern-driven design correction, analysis and verification. Learn More

IC Design Tools

Digital IC Design

Mentor Graphic's IC implementation system, Olympus-SoC, delivers innovative technologies for fast and high-quality design closure at advanced process nodes.

Analog/Mixed-Signal Verification

Mentor Graphics offers industry leading high-performance simulation and verification solutions for complex analog/mixed-signal System-on-Chip designs.

Calibre Design for Manufacturing

Building on our powerful, production-proven Hyperscaling architecture, Calibre delivers the broadest, most accurate, and best performing DFM solutions in the industry.

Calibre IC Verification & Signoff

Mentor Graphic's IC verification and sign-off includes traditional rule-based physical verification, parasitic extraction, and automated technologies that help improve yield.

Custom IC Design

Mentor Graphics offers integrated solutions for design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout and chip assembly.

Silicon Test and Yield Analysis

The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug and yield ramp for today's SoCs. Learn more about Silicon Test and Yield Analysis

White Papers

Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?

Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper

High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also... View White Paper

Integration of Pattern Matching© into Verification Flows

In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it... View White Paper

On-Demand Events

Deep Submicron Solutions - Division Overview

Technology Overview: The Deep Submicron Division is meeting the needs of complex Analog and Mixed Signal design and verification with dramatic productivity improvements through unique automation plus advanced features to reconcile... View Technology Overview

Overcoming Complexity in the Physical Verification Signoff Process

On-demand Web Seminar: As we progress to ever smaller nodes, the number of rule checks keeps growing along with the complexity of the rules. Custom and AMS designers are experiencing more and more iterations, slowing down the... View On-demand Web Seminar

Foundry Partners

Foundry Partners

Mentor Graphics has teamed up with the world's top foundries, including Chartered, Donbgu HiTek, IBM, TSMC, and more, to jointly develop and qualify Calibre DRC, LVS, and PEX rule files.