IC Design and Circuit Design Verification
The Most Comprehensive IC Implementation
Environment Available
Mentor Graphics offers the most comprehensive IC implementation environment available today. Our solution combines the ground-breaking Olympus-SoC™ place-and-route system, the industry-standard Calibre® physical verification and design-for-manufacturing product suite, and our award-winning integrated platform. These industry-leading products provide a comprehensive “Design-to-Silicon” solution.
Hands-on Learning: Calibre Verification Workshop
Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing. Calibre Design-to-Silicon Platform Workshop
Manufacturing Variability Solutions
Our tools extend across the entire physical implementation lifecycle, starting with cell library development, and continuing through place and route, physical verification, layout optimization, mask preparation, testing and failure analysis. Manufacturing Variability Solutions
Olympus SoC
Olympus-SoC™ place-and-route system wins the 2009 DesignVision Award at DesignCon 2009. Learn more about Olympus-SoC
IC Design Tools
Olympus Place-and-Route System
Mentor's IC implementation system, Olympus-SoC, delivers innovative technologies for fast and high-quality design closure at advanced process nodes.
AMS Design, Verification and Layout
Mentor delivers a set of AMS design tools built on the ICStudio platform to address design, verification and layout in an efficient, integrated way.
Calibre DFM Platform
Building on our powerful, production-proven Hyperscaling architecture, Calibre delivers the broadest, most accurate, and best performing DFM solutions in the industry.
Calibre IC Verification Platform
Mentor's IC verification and sign-off includes traditional rule-based physical verification, parasitic extraction, and automated technologies that help improve yield.
Techpubs and Resources
IC Design Techpubs
Implementation-Quality Prototyping with Olympus-SoC: Accelerating Design Closure for Advanced ICs
Techpub: The growing complexity of today’s ICs and tight market schedules are driving a demand for more powerful solutions for design prototyping. Prototyping helps designers determine the feasibility... View Techpub
Critical Feature Analysis as Golden Path to DFM Closure
Techpub: This paper discusses the features implemented in a Design for Manufacturability (DFM) checker for Critical Feature Analysis of Very Deep Sub-Micron (VDSM) layout designs. This checker leverages... View Techpub
TrustMe-ViP: A Virtual RF System Platform Project for TPD
Techpub: Shrinking feature sizes and advanced fabrication technologies enable IC designers to integrate more functionality onto a single chip (SoC: System on Chip), in particular in the Trusted... View Techpub
Foundry Partners
Mentor Graphics has teamed up with the world's top foundries to jointly develop and qualify Calibre DRC, LVS, and PEX rule files. These rule files encompass foundry standards and are available directly from the foundry. Foundry Partners
Consulting Services
Customized solutions to technical challenges on real projects with real schedules. By helping customers successfully integrate Mentor technologies and methodologies into their work flows, we help ensure they meet their design and business objectives. Mentor Consulting
Customer Success
"Calibre offers a unique combination of performance, accuracy, and capability allowing us to implement an optimal recipe for our 0.095 micron process. Calibre is already in use with our 0.180 and 0.150 micron technologies, and NEC is aggressively moving forward with advanced semiconductor processes. Calibre is a key enabler in accelerating this schedule."
Dr. Kazuhiko Takamizawa, Senior Manager of System LSI Design Engineering Division. Customer Quotes
Customer Success
"STMicroelectronics is a leader in delivering a complete CMOS 32nm design solution to our customers that optimizes design productivity for low power designs without compromising the performance, quality or the silicon correlation. To achieve this goal, we have built a reliable ecosystem with our long term partner, Mentor. We worked together to develop a robust solution for the design and characterization of our libraries for our worldwide design teams," said Gérard Mas, CMOS Libraries Group Director of the Technology Research and Development group at STMicroelectronics.
Press Release
From the Blogs
How to MV in 10 easy steps (really over simplified backend flow)
Step 0 Commitment – Are you really sure you want to MV? Are you positive that Multi-Vt & Clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.
Step…View Blog Post
Pattern Matching Might Solve World Hunger
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks…View Blog Post
News & Press
- Leading Semiconductor Suppliers Use Calibre PERC to Check for Protection Against Catastrophic Electrical Circuit Failures
- Mentor Graphics Calibre PERC Named Product of the Year by Electronic Products Magazine
- Freescale Semiconductor Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM
- Juniper Networks Completes World’s First Network Instruction Set Processor Design Using Mentor Graphics Calibre and Design-for-Test Solutions
- More