IC Design
Mentor Graphics offers the most comprehensive IC design, verification, DFM and test technologies available today.
Our technologies address the most pressing challenges facing IC development teams for custom analog and digital, digital place and route, mixed-signal and system-on-chip (SoC) designs. Tight collaboration with foundries, IC design houses, systems companies, research and development labs, and industry standards organizations ensures our tools meet state-of-the-art requirements and deliver real competitive value.
IC Design Tools
Digital IC Design
Mentor Graphic's IC implementation system, Olympus-SoC, delivers innovative technologies for fast and high-quality design closure at advanced process nodes.
Analog/Mixed-Signal Verification
Mentor Graphics offers industry leading high-performance simulation and verification solutions for complex analog/mixed-signal System-on-Chip designs.
Calibre Design for Manufacturing
Building on our powerful, production-proven Hyperscaling architecture, Calibre delivers the broadest, most accurate, and best performing DFM solutions in the industry.
Calibre IC Verification & Signoff
Mentor Graphic's IC verification and sign-off includes traditional rule-based physical verification, parasitic extraction, and automated technologies that help improve yield.
Custom IC Design
Mentor Graphics offers integrated solutions for design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout and chip assembly.
Silicon Test and Yield Analysis
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug and yield ramp for today's SoCs. Learn more about Silicon Test and Yield Analysis
White Papers
High Speed, Accurate AMS Simulations Reduces Transient Noise in Complex CMOS Circuits
As implementable analog circuit size has increased significantly due to advancements in manufacturing process, analog designers of system large scale integration (LSI) face increasingly difficult problems.... View White Paper
An Innovative Approach to High Frequency Analysis of IC Layouts
Traditional high frequency analysis (HFA) of integrated circuit designs is based on an empirical approach, which is slow and cumbersome. It is costly to develop the initial model for an IC process, and... View White Paper
Achieving Fast and Accurate Extraction of 3D-IC Layout Structures
The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition... View White Paper
On-Demand Events
How to automatically replace LEF abstracts with GDS IP in Calibre Physical Verification for LEF/DEF input Overview: Physical Verification or other downstream analysis flow of P&R design data which only... View Video
This video will demonstrate how to edit the polygons at certain instances of the design from the top-level in order to fix some DRC violations. View Video
Foundry Partners
Foundry Partners
Mentor Graphics has teamed up with the world's top foundries, including Chartered, Donbgu HiTek, IBM, TSMC, and more, to jointly develop and qualify Calibre DRC, LVS, and PEX rule files.