Mentor Graphics offers the most comprehensive IC design, verification, DFM and test technologies available today.
Mentor Graphics Training
We have training courses available for IC Design in our training centers around the world, online, or at your site.
Providing dramatic productivity improvements and unique functionality including constraint based custom routing and concurrent editing. Learn more
On-demand Calibre Signoff Verification in Custom Design Flows. Learn More
High performance extraction engine integrated into design flows reference-level accuracy. Learn More
Delivering true signoff analysis and automatic DRC/DFM fixes during implementation. Learn More
IC Design Tools
Mentor Graphic's IC implementation system, Olympus-SoC, delivers innovative technologies for fast and high-quality design closure at advanced process nodes.
Mentor Graphics offers industry leading high-performance simulation and verification solutions for complex analog/mixed-signal System-on-Chip designs.
Mentor Graphic's IC verification and sign-off includes traditional rule-based physical verification, parasitic extraction, and automated technologies that help improve yield.
Mentor Graphics offers integrated solutions for design capture, floorplanning, custom routing, polygon editing, physical layout, schematic-driven layout and chip assembly.
As implementable analog circuit size has increased significantly due to advancements in manufacturing process, analog designers of system large scale integration (LSI) face increasingly difficult problems.... View White Paper
Traditional high frequency analysis (HFA) of integrated circuit designs is based on an empirical approach, which is slow and cumbersome. It is costly to develop the initial model for an IC process, and... View White Paper
The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition... View White Paper
How to avoid cell name conflicts in chip assembly with automated cellname prefix/suffix
In today’s complex chip design flows, designers receive libraries with physical data from multiple internal and external vendors. The potential for having a cell-name conflict between different libraries... View Video
How to automatically replace LEF abstracts with GDS IP in Calibre Physical Verification for LEF/DEF input Overview: Physical Verification or other downstream analysis flow of P&R design data which only... View Video