Time-it Delay Calculator
Time-it is an independent delay calculation tool that is used in a back-end design flow with the Mentor Graphics analog/mixed-signal tool suite. It accepts parasitics information from extraction tools like Calibre® xRC, calculates delay information and generates an SDF file for back-annotation to timing-accurate simulation and static timing analysis.
As a command-line calculator, Time-it allows you to calculate the cell and interconnect delays for your designs simulated with Mentor Graphics ModelSim® and Questa ADMS™, and provides a common method for importing accurate delays into synthesis, simulation and static timing analysis.Fits into any cell-based design methodology
- Fits into any cell-based design methodology
- Accurately models the interdependency between RC interconnect effects and the driving capability of the cell
- Reduces computational time while improving accuracy
- Provides significant speed, accuracy and capacity benefits
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.
ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.
Language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs.