Kronos Characterizer Plus
Cell Library Characterization
Kronos Characterizer Plus is a high-throughput, general purpose cell library characterization tool for standard cells, memory, IO Pad, and custom macros.
Features and Benefits
- Characterize an entire library in days instead of weeks with highly efficient, parallel algorithms
- Optimize and debug complex circuits in minutes with a unique, graphical, single-step mode and integrated waveform analysis
- Don’t buy what you already have… Kronos is not packaged with a simulator; instead it takes advantage of existing simulation licenses.
- High Performance Integration with Eldo Classic
- All-in-one solution: integrated platform for cell library characterization of standard cells, memory, I/O, and complex cells
- Easy memory cell configuration
- Automatic memory characterization: netlist reduction, fast simulation techniques, creation of complete Liberty models for all corners
- High throughput with fast turnaround time and multi-simulation job control
- Build new or re-characterize existing libraries
- Create state-dependent models for timing and power
- Supports Liberty, Verilog, VHDL/VITAL
- IBIS model generation and validation
- NLDM, CCS, and ECSM model generation
- Accurate timing, power, and noise models
- Interfaces with Kronos Analyzer for library validation, analysis, and reporting
- Complete user control of configurations and output model formatting
Kronos Characterizer Solutions
Cell Library Characterization
Without correctly characterized libraries, an entire design project and millions of dollars in design and fabrication time may be at risk. Designing at the wrong environmental corner or not taking advantage of a special operating voltage may lead to a slower, larger design that wastes power or takes much longer to close timing.
Kronos Characterizer Plus quickly produces accurate performance models for standard cells, memory, I/Os, and complex cells within an advanced, integrated environment. It characterizes timing, power, and noise for design synthesis and timing verification systems.
Kronos Characterizer Plus is able to generate Liberty and Verilog/Vital models for a wide variety of cells. Large circuits, such as memories, are nearly impossible to simulate directly with an analog circuit simulator. However, it is possible to generate a subset of the original netlist that accurately represents the entire memory behavior because usually only a small portion of a memory is active during typical operations. Since characterization involves running a large number of circuit simulations at different input and output conditions with the same core netlist, netlist reduction can result in a tremendous CPU time reduction and greater accuracy.
Kronos Characterizer Plus introduces a netlist trimming flow that first performs simulation using a fast SPICE simulator, such as ADiT™, or a faster SPICE simulator, such as Eldo® Premier, to reduce the netlist based on node activity and netlist structure. Since characterization involves running a large number of circuit simulations at different input and output conditions with the same core netlist, netlist reduction can result in a tremendous CPU time reduction and greater accuracy.
Kronos Characterizer Plus works with Kronos Analyzer, which enables designers to compare the effects of SPICE model changes, layout changes, and cell performance optimizations. It also validates characterized libraries against previous library versions and/or against golden models.
Versatile Model Creation and Support
Kronos Characterizer Plus’s advanced algorithms and efficient job distribution reduces characterization time from weeks to days. Complex flip-flops that would normally take 30 minutes to complete on a single machine can finish in as little as one minute. During characterization, SPICE simulations are continuously monitored. Numerous data checks and recovery mechanisms significantly improve turn-around time by pinpointing specific model results.
At 45 nm and below, speed and power consumption are much more sensitive to environmental conditions, including voltage and noise. Producing accurate models at the appropriate conditions is critical to achieving design success. Kronos Characterizer quickly generates accurate and complete timing and power models. It incorporates proprietary methods for noise immunity and signal integrity to avoid design problems that otherwise might not be detected until failure analysis. Kronos Characterizer creates accurate timing models using correct input patterns and realistic waveforms.
Kronos Characterizer Plus has a highly customizable modeling environment that gives the user complete control of input stimulus and pattern sequencing. Bus pin models and pin aliases provide the versatility to create precise IO Pad libraries with all the required worst-case representations. Because Kronos Characterizer is a general-purpose modeling system, advanced models can be created for any circuit. Advanced Kronos Characterizer technology enables building Synopsys CCS or Cadence ECSM models that are improved for timing accuracy and power—especially critical for 90 nm and below.
Kronos Characterizer Plus supports Liberty advanced power models, for level shifters and other power control techniques, as well as Verilog, which contains user-defined primitive (UDP) statements for power pins and power gating. An option for building Liberty noise models creates noise immunity and propagation data.
A versatile state-dependent specification system creates state-dependent models for timing and power. An integrated waveform viewing environment allows users to rapidly identify problems in circuit behavior and works with all supported simulators. This environment also provides a true, real-time view into the object-oriented library configuration.
Kronos Characterizer Plus can be quickly and easily configured by importing an existing library. Kronos Characterizer uses formal mapping methods when importing cells and handles all technology setup. Custom models are created using Kronos Characterizer’s versatile and efficient object methodology. Mentor provides extensive examples for modeling complex sequential cells and many other components.
Eldo Classic from Mentor Graphics is the preferred SPICE simulator for Kronos Characterizer. The integration between Eldo Classic and Kronos Characterizer is optimized to take full advantage of Eldo Classic’s performance, accuracy, and quick elaboration. Kronos is also integrated with Synopsys HSPICE simulator.
Kronos Characterizer Plus enables designers to check data completeness against expected results and cross-checks library views with built-in validation utilities. HTML or PDF datasheets can be produced from user customizable TCL templates with the Kronos Characterizer datasheet generator. User-specific report or dynamic web-query can be created, and Verilog, Vital, and VHDL front-end views generated.
Kronos Analyzer is a comprehensive library analysis and validation solution.
When accuracy matters designers choose Eldo Classic, Mentor’s “golden” SPICE accurate circuit simulator, designed to address the complex needs of analog and mixed-signal designers.