Questa ADMS RF
Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems
Complete simulation of RF system-on-chip (SoC) designs becomes a reality when you combination the RF capabilities of Eldo RF with the mixed signal capabilities of Questa ADMS. Built upon these solid foundations, the Questa ADMS RF solution allows effective simulation of communication systems containing tightly linked RF and baseband functions—analog and digital.
Questa ADMS RF uses industry-standard languages only. SPICE, VHDL, Verilog, Verilog-A and VHDL-AMS. Reuse of legacy code is thus greatly simplified. An existing Questa ADMS design can be imported in a matter of seconds, without any modifications, and simulated along the transistor-level mixers and VCOs of the RF front-end, whatever the feedback and control loops. It also uses advanced mixed time-frequency algorithms which computes a time-varying spectrum. The spacing of time points is chosen to follow the slow-varying baseband information, rather than the fast-varying RF carriers. These algorithms have the same accuracy as regular but slow circuit-level transient simulation This results in huge speedup ratios over regular transient simulation, without compromising accuracy.
Features and Benefits
- Decrease Risk: More complete verifications of complex RF SoC for wireless communication applications minimizes risks of faulty RF/baseband connections.
- Decrease Simulation Time: Simulates complete systems orders of magnitude faster than previous tool generation. Many more operating conditions can be verified.
- Improve Accuracy: Questa ADMS RF preserves transistor-level accuracy wherever it is necessary.
- Improve Productivity: Uses industry-standard languages only, and no proprietary languages. Reuse of unmodified legacy code is greatly facilitated.
- Improve Integration: RF and baseband IC designers can start working together, with the same tools, much earlier in the design process. Productivity is enhanced.
- Uses SPICE, VHDL, Verilog, Verilog-A.
- Integrated RF and mixed-signal baseband simulation.
- Immediate reuse of HDL legacy code.
- Critical RF blocks can be described with full transistor-level accuracy.
- Behavioral RF modeling in Verilog-A.
- Efficient time-frequency domain simulation with multi-GigaHertz carrier frequencies.
- Integrated in the Mentor IC Flow and in Cadence ADE environments.
- Familiar ADMS interface for a shorter learning curve.
We have training courses available for Questa products in our training centers around the world, online, or at your site.