Calibre nmDRC
Overview
Calibre® nmDRC addresses the physical verification challenges of nanometer designs with a new Hyperscaling architecture that provides best-in-class DRC run times with scalability to 100 CPUs. Full compatibility with popular layout environments and direct read capability allow designers to invoke DRC and debug results seamlessly within their design flow. Calibre nmDRC leverages the Calibre nm Platform to provide model-based verification and analysis, and visualization to guide you to the errors that truly impact yield. Innovative incremental verification, and a dynamic results viewing and debugging environment further reduce DRC cycle time and dramatically improve your productivity.
Calibre's new Equation-Based DRC (eqDRC) capability fills the void between traditional DRC and DFM process simulators, bringing user extensibility and fast runtimes to a whole host of new design and process interactions. Identifying and prioritizing design layout issues that affect yield are a big drag on turnaround time. Some issues are simply too complex to capture with traditional DRC measurements, and traditional DRC provides little understanding of which factors cause manufacturing failures. Equation-based DRC enables accurate characterizations of complex, multi-variable interactions that have a direct impact on manufacturability. This allows you to make reliable design tradeoffs, and to quickly determine the best fix.
Collateral
- Datasheet: Calibre nmDRC (pdf, 483kb)
- Datasheet: Calibre eqDRC (pdf)
- Customer Results: nmDRC Hyperscaling Results View Results
Evaluation Software
Key Benefits
Calibre DRC is the industry standard with over 900 customers since 1996, and is used at all Tier-one foundries, the top IDMs, and more than 500 fabless companies.
- Fast turnaround: Hyperscaling provides fast DRC run time and high CPU scalability
- Advanced checking: Equation-based DRC enables advanced checking without complex rule decks for reduced area and improved tolerance to manufacturing variability
- Parallel debugging: Speeds identification, analysis and correction of violations by enabling a concurrent work flow
- Faster time-to-yield: Model-based verification, analysis, and visualization guide you to the errors that truly impact yield
- Investment protection: Straight drop-in to existing DRC flows. Leveraging over 3.5 million lines of SVRF code from 250nm to 45nm process nodes protects your investment in flow infrastructure, training, and rule decks
- Support: the only 5-Star support in EDA
Technical Publications
A New Approach to Sign-Off
Along came nanometer process technology, where increasing rates of silicon failure and longer yield ramps initiated a sea change in how designers deal with process constraints. Designers now find they can no longer adequately describe the effects of process limitations and variations using design rules alone. Most urgently, compliance with design rules no longer always guarantees acceptable yields. Here is why...
View Tech PaperPower of a Platform in the Nanometer Era
As design becomes more complex, process variation becomes more difficult to control, and acceptable cycle time becomes less attainable, the design and manufacturing communities look to EDA for solutions that can help manage outcomes. But what is a platform? And, is it the answer to the problems of the nanometer era?
View Tech PaperEvolution of the Calibre Architecture
In industry and the marketplace, new products are often advertised as revolutionary. Although the next big thing may seem unique and innovative, new products are often the evolution of current technology. In EDA, a revolution in technology often means a disruption of established work flows.
View Tech PaperDRC in the Nanometer Era
In the nanometer era, DRC is no longer just a pass/no pass routine. It has evolved into a whole new way of managing comprehensive analysis, incremental verification, efficient debugging and improved cycle times.
View Tech PaperOnline Events
Revolutionizing DRC: Calibre nmDRC
At 90 nm and below, the dramatic increase in the number and complexity of DRC rules is taking a toll on DRC cycle time: from first-pass through tape-out clean. Mentor Graphics has a soluion - Calibre nmDRC. Please view and learn more about the revolutionary changes that transformed Calbire DRC into Calibre nmDRC.
Online NowFrom DRC Clean to DFM Optimized
This online seminar covers how you can benefit from the latest in Calibre physical verification and design for manufacturing technologies. From a history of DRC and LVS to upcoming trends DFM and nanometer silicon modeling, this seminar will show views how the Calibre tool suite is continuing to lead the way
This seminar also discusses the evolution of the Calibre engine and how our integration with all major 3rd party database formats enables design innovation.
Online NowReducing Calibre DRC Runtimes Through Scaling
You're familiar with Calibre and it's capabilities, but are you truly getting the most out of the tool? Watch this online seminar to gain valuable insights on how to use the current functionality of Calibre to address the performance and capacity challenges of today's complex designs.
Online NowNews
Calibre nnDRC: In The News
- Success Story: Atmel Increases Yield While Reducing Time-to-Market and Design Costs with Mentor Graphics Calibre nmDRC, LVS and xRC
-Atmel/Mentor Graphics, Oct 10, 2007 - Press Release: Agere Systems' Storage Division Readies for 65 Nanometers with Adoption of Mentor Graphics Calibre
-Mentor Graphics, Sept 12, 2006 - Industry Article: Reducing Cycle Times for Design Rule Checking
-EE Times, July 31, 2006 - Press Release: Mentor Graphics Calibre nmDRC Delivers Superior Productivity on the Intel Dual-Core Xeon 5160 Processor
-Mentor Graphics, July 27, 2006 - Press Release: Mentor Graphics Calibre nmDRC Supports the AMD Opteron Processor
-Mentor Graphics, July 27, 2006