Calibre nmLVS
Calibre® nmLVS, the market-leading layout vs. schematic physical verification tool, is tightly linked with both Calibre nmDRC and Calibre xRC to deliver production-proven device extraction for both physical verification and parasitic extraction. Calibre nmLVS performs a vital function as a member of a complete IC verification tool suite by providing device and connectivity comparisons between the IC layout and the schematic. Calibre's hierarchical processing engine runs Calibre nmLVS, supplying data for modifying the IC design to achieve superior functionality and reliability. Calibre nmLVS enables accurate circuit verification because it is able to measure actual device geometries on a full-chip for a complete accounting of physical parameters. These precise device parameters supply the information for back-annotation to the source schematic and the comprehensive data for running simulations. In addition to working with Calibre xRC, Calibre nmLVS can also be used with third party parasitic extraction tools.
Calibre's ability to interactively verify and make corrections in an existing design framework, without being constrained by proprietary tools or flows, dramatically reduces iteration runtime and error debugging. This robust and easy-to-use integration enables designers to use Calibre as a single platform for cell/block and full-chip verification, as well as parasitic extraction.
Key Benefits
- Market Leadership - Calibre nmLVS continues to lead the market. Preferred by engineers and management for its proven performance, capacity, reliability and debug ease-of-use.
- Best-in-Class Accuracy - Device recognition accuracy is crucial for tape-out success. Calibre nmLVS delivers the trusted device recognition accuracy and timely execution required for world-class silicon delivery.
- Fast Runtime - Automated proprietary hierarchical and logic injection technologies provide virtually unlimited design scope with fast runtimes. Multi-threaded and distributed CPU processing capabilities ensure future proof scaling on your hardware.
- Flexibility - Calibre nmLVS is ideally suited for processing any size job requiring intricate device parameter extraction, whether it’s an analog/RF design or a multimillion gate IC.
- Reliability - With thousands of users, Calibre nmLVS sets the standard for reliability and predictability in all operations.
- Design Debugging and Ease-of-Use - Calibre nmLVS provides an intuitive and easy-to-use integrated design verification debugging environment to help you find and fix design issues. Calibre® nmLVS is two to three times faster than traditional layout vs. schematic processes.
Technical Events
Calibre nmLVS Integrated Design Debug Environment Demonstration
This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow. View now!
Live Webex: Reducing Cycle Time in Physical Verification
As critical dimensions shrink below 65nm, yield becomes more sensitive to manufacturing variability. More complex and numerous design rule checks (DRCs) are needed to ensure designs can be efficiently realized in fabrication. At the same time, the sheer size of new designs causes DRC run times to grow exponentially. More complex design rules result in many more DRC violations that are more difficult to find, so engineers must spend more time fixing and re-checking their physical designs. Attend this online seminar and learn how to reduce cycle time in physical verification. Register Now!
Press/News
- Reducing time in IC physical verification July 15, 2008 - SCDSource
- Mentor Graphics Aligns Product Groups to Address IC Implementation Challenges at 45nm and Beyond May 7, 2008
- Toshiba Selects Mentor Graphics Calibre DFM Platform for its Device Extraction Flow May 19, 2008
- Improving productivity and nm nodes with faster physical verification February 2008 - SolidState Technology
- Layout-Aware Compact Model of MASFET Characteristics Variations Induced by STI Stress Volume E91-C, Number 7 - IEICE (NOTE: EICE Subscription Required)