Pinnacle: Solution

While Moore's Law has quadrupled chip capacity in moving from 180 to 90 nanometer processes, IC implementation tool capacity for overnight closure has stagnated, resulting in delayed schedules and higher design resource costs. At 90nm, 65nm, and below, designers being forced to juggle the challenge of controlling the macro-level functional complexity issues (operational modes) and the micro-level process and manufacturing issues (corners) while trying to meet time-to-market targets.

Designers have been addressing the issues of multiple chip operating contexts and process variations by painful constraint merges and guessing design margins and worst-case corner conditions during the early phase of the design implementation. During the later phases of the design cycle, these last-generation implementation flows force designers to manually analyze and fix the effects of all other mode/corner combinations in an iterative and non-convergent process. This is a very unpredictable process that frequently leads to missed schedules or reduced performance.

Existing physical synthesis approaches rely extensively on computationally expensive techniques, such as iterative improvement and brute force trial-based optimization resulting in unacceptably long turnaround time. In addition, traditional prototyping approaches are inaccurate since their product architectures are decoupled from the final implementation systems. This results in miscorrelated timing and congestion analysis and an inability to predict the final performance after implementation.

The Pinnacle Solution

Pinnacle suite analysis provides a high correlation with industry-standard timing sign-off tools. The Adaptive Variability Engine automatically analyzes DFV issues and drives optimizations throughout the implementation flow, including floor planning, feasibility, placement, optimization, clock tree synthesis, and routing.

Mentor has developed a new patent-pending physical synthesis approach that gives highly-optimized results for multi-million gate flat designs in a single overnight run. The Detailed Native Analysis Kernel is a unique architecture enhancement that makes sign-off quality timing, extraction, and delay calculation "native" to the Pinnacle kernel. This enables Pinnacle to handle any number of timing views of the design with minimal impact on runtimes and memory requirements.

Shorter Turnarounds

Pinnacle's dramatically shorter turnaround time also results from new technological advances in the area of performance bottleneck detection and analytical optimization. This new approach to physical synthesis is helping Mentor's customers achieve design closure on multi-million gate designs in a fraction of the time of required for existing design flows.

Pinnacle's ultra-compact database has the industry's highest scaling capacity and the smallest memory footprint. This enables both feasibility analysis and final implementation in the same unified environment resulting in very high correlation throughout the flow. Pinnacle also addresses the complex challenge of constraint validation for "dirty" design data using proprietary physical synthesis technology that is robust in the presence of ill-formed constraints.