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IC Design Blog

18 Aug, 2014

Testing the Boundaries of Good Design

Posted by Shelly Stalnaker

Shelly Stalnaker In a SPIE.TV interview, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon division of Mentor Graphics, explains the challenges of moving from design abstraction to physical implementation to a successful yield. “Design to silicon” is a complex process that continuously blends evolutionary trends, such as enhancements to 3D mask design and yield learning, with more … Read More

14 Aug, 2014

Shelly Stalnaker Design-style-based (systematic) defects are the major challenge to yield ramp at advanced process nodes, adding to the complexity of the basic process ramp. Because of its involvement in the design, manufacturing, and test, EDA is in a unique position to contribute toward the control, if not the solution, of this problem, through the use of automated pattern detection and analysis. Patterns can be useful … Read More

7 Aug, 2014

Failing to Succeed

Posted by Shelly Stalnaker

Shelly Stalnaker Failure analysis is a critical process in successful IC production. No matter how comprehensive the design rules are, no matter how thorough the verification strategies are, there will be chip failures in production. Understanding the cause of these failures is crucial to being able to implement design strategies and corrective technology to ensure the failures are eliminated in future designs. At its … Read More

22 Jul, 2014

Global Warming

Posted by Shelly Stalnaker

Shelly Stalnaker If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation … Read More

21 Jul, 2014

Won't You Please, Please Help Me?

Posted by Shelly Stalnaker

Shelly Stalnaker No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!! And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is … Read More

10 Jun, 2014

Goooaaaaaaaaaaaaal!

Posted by Shelly Stalnaker

Shelly Stalnaker The World Cup is here! Every four years, the culmination of hundreds of qualifying matches around the world brings the best national teams together for nearly a month of intense competition to determine the world champion football team (Sorry, USA, but it’s football everywhere else). New national uniforms are unveiled, shoe companies vie to sponsor the best players and teams with their most advanced … Read More

IC Verification, ic manufacturing, Mentor Graphics, DRC, DRM, Design Rules, Foundry, process flow, IC Design, Fabless

13 May, 2014

Shelly Stalnaker With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased … Read More

P&R, Olympus-SoC, place and route, 16nm, 20nm, 10nm, IC Design, Multi-Patterning, double patterning, FinFET

8 May, 2014

Lights! Camera! Multi-Patterning! Take Two!

Posted by Shelly Stalnaker

Shelly Stalnaker Remember learning your colors in kindergarten? Learning how to debug color assignment errors in multi-patterning can sometimes seem just as confusing. In Take Two of the Tech Talk videos on multi-patterning, David Abercrombie continues his discussion with Brian Bailey of Semiconductor Engineering about color assignment issues, and possible corrective actions. More often than not, a color assignment … Read More

David Abercrombie, design debugging, Calibre, IC Verification, Multi-Patterning, double patterning, IC Design

7 May, 2014

Sinkhole or Springboard?

Posted by Shelly Stalnaker

Shelly Stalnaker Depending on how well your company implements it, verification can be a quagmire that slows down your design delivery and creates frustration and conflict between teams, or a springboard that lets you deliver high-quality designs ahead of your competition. In a recent interview with Pradeep Chakraborty, our CEO, Wally Rhines, discusses the intricacies of design verification today, the biggest verification … Read More

Semiconductors, Mentor Graphics, SoC, 16 nm, 20nm, 14nm, Walden C. Rhines, IC Design, Wally Rhines, IC Verification, design verification

21 Mar, 2014

I See the Light!

Posted by Shelly Stalnaker

Shelly Stalnaker Photonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design. The biggest challenge in applying CMOS foundry processes to silicon photonics is creating … Read More

Foundry, IC Design, silicon photonics, waveguides, ic manufacturing, Michael White

19 Mar, 2014

Déjà Vu All Over Again

Posted by Shelly Stalnaker

Shelly Stalnaker Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm … Read More

Foundry, IC Design, 14nm, 16nm, 10nm, advanced node, leading-edge, Semiconductor, Christen Decoin, 20nm, technology node, 28nm

18 Mar, 2014

Old Faithful

Posted by Shelly Stalnaker

Shelly Stalnaker While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More

IC Design, IC Verification, 16nm, 20nm, 10nm, circuit, PERC, Reliability, electrical, 45nm, Verification, Calibre

14 Mar, 2014

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

3 Mar, 2014

Lights! Camera! Multi-Patterning!

Posted by Shelly Stalnaker

Shelly Stalnaker David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More

double patterning, EUV, 20nm, Multi-Patterning, triple patterning, IC Design, ic manufacturing

19 Feb, 2014

Shelly Stalnaker The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the … Read More

IC Design, IC Verification, dynamic power grid analysis, vcd, vectorless verification, power grid analysis, value change dump

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