With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased design sizes, and multiple design objectives can seem overwhelming, especially when your time-to-market targets get shorter every day.
What designers need is a flexible and powerful architecture that addresses multi-patterning and FinFET requirements while still helping design teams achieve optimal power, performance, and area across all design metrics. Our new white paper, FinFET and Multi-Patterning Aware Place & Route Implementation, provides a detailed discussion of the challenges presented in design implementation at advanced nodes, giving you a raft that will help you overcome the myriad challenges and bring your designs safely ashore.