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A Raft for a Flood - FinFET and Multi-Patterning Aware Place & Route

Olympus-MP-buildWith the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased design sizes, and multiple design objectives can seem overwhelming, especially when your time-to-market targets get shorter every day.

What designers need is a flexible and powerful architecture that addresses multi-patterning and FinFET requirements while still helping design teams achieve optimal power, performance, and area across all design metrics. Our new white paper, FinFET and Multi-Patterning Aware Place & Route Implementation, provides a detailed discussion of the challenges presented in design implementation at advanced nodes, giving you a raft that will help you overcome the myriad challenges and bring your designs safely ashore.

P&R, Olympus-SoC, place and route, 16nm, 20nm, 10nm, IC Design, Multi-Patterning, double patterning, FinFET

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About Shelly Stalnaker

Shelly StalnakerI believe in the well-written sentence, the eye-catching title, and the satisfaction of hearing someone say, “Now I get it.” I believe there ought to be a constitutional amendment outlawing the use of the passive tense in technical writing. I believe a writer can explain and entertain at the same time, and I believe that everyone, even in the business world, has a story to tell. Visit Foundry Solutions

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