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Are Design Rules Broken?

It is no mystery that the number of design rules has exploded over the past few technology nodes. It’s impossible for any human designer to “remember” them all, much less follow them all. It’s also a problem for the CAD engineer. We extracted some data from a spectrum of DRC decks that our customers have in production and the graph below shows the results.

DRC Rule Count and Complexity by Technology Node

DRC Rule Count and Complexity by Technology Node

The rule count is increasing, but maybe more surprising the Calibre operation count has gone up even faster. This increase in operation count is due to the fact that the rules themselves are more complicated. Despite all these rules with all this complexity, we are hearing from customers that design issues are slipping through the net and causing problems in manufacturing.

I believe that two primary issues are driving this problem. The first is a very practical issue of overspecification. There are so many rules with so much interaction that no one can even tape out DRC clean any more. We have heard from a large number of our customers that they no longer even expect to tape out DRC clean. Essentially, it is so complicated they can’t deal with the situation. They have developed informal systems for requesting waivers from the foundry. It seems like some kind of heresy to even suggest that you might consider taping out with DRC errors and even more heresy that the foundry would say ok. However, it happens because of the second bigger issue which is that the rules themselves don’t work in the first place.

In today’s advanced technology nodes, the robustness of a particular layout feature can no longer be determined accurately by the traditional single dimensional pass/fail constructs that design rules and design rule checkers have depended on. For example, how far apart should two metal 1 shapes be? In the “good old days” then answer would have been some minimum dimension X. However, today the answer would be best summed up with two words; “It depends”. Is it a line end? How wide are the metal shapes? what is the concurrent run length of the adjacent shapes? See the example drawing below. As you can tell, the answer is becoming multi-dimensional and sometimes X is ok, sometimes X is tool small causing yield loss and sometimes X is too big causing loss of area compaction.

Single-dimensional rule requirements vs multi-dimensional rule requirements

Single-dimensional rule requirements vs multi-dimensional rule requirements

The result is that the foundries attempt to compensate by creating 100’s of separate single dimensional rules to cover all the corner cases. This, in turn, creates severe over constraint that the designer can’t meet, and since the foundry knows they have overconstrained the problem they are prone to giving in to waiver requests. The simplicity of single dimensional DRC rules forces us into following the “letter of the law” without capturing the “spirit of the law”. It starts to feel like we let a room full of lawyers into the design center.

The question for you is do you agree or am I over reacting? Have you encountered these issues? What types of things have you seen? What do you think is wrong? How much time are you wasting on rules or violations that you end up waiving anyway? Have you had a design pass DRC and fail in manufacturing for some layout feature? How much do you think your layout area is being impacted by these “bad” rules?

Should we stage a strike or lauch rockets?

Physical Verification, Design Rules, DRC, Design Rule Checking

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About David Abercrombie

David AbercrombieI am the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last five years at Mentor I have been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. For the previous 15 years I drove yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. I also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. I hope you will read my publications and patents on semiconductor processing, yield enhancement and EDA verification solutions. I received my BSEE from Clemson University in 1987 and my MSEE from North Carolina State University in 1988. I love to play the guitar, explore the great outdoors, and watch a great science fiction show. Visit David Abercrombie’s Blog

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