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Battle of Fins and BOXes

Do FDSOI and FinFET technologies provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI?  Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits but there is no clear winner yet as these are relatively new technologies that are still maturing and its too early to call.

FDSOI or Fully Depleted Silicon on Insulator (FDSOI) technology relies on a thin layer of silicon that is over a Buried Oxide (BOx). Transistors are built into the thin silicon layer that is fully depleted of charges and hence provides some unique advantages over bulk.

Cross section of a FDSOI transistor

FDSOI technology claims better power and better performance than its bulk counterpart. Since the body is fully depleted the random dopant fluctuation that plagues bulk CMOS is reduced which  helps improve performance even at lower VDD. Power/performance claims of 30% to 40% are not uncommon and FDSOI is already in production at 28nm and is positioned as an alternate option to  bulk 20nm. Even if FDSOI at 28nm delivers half the power savings of bulk 20nm, I would take it any day rather than dealing with the beast that is Double Patterning. I digress. One of the other untold  benefits from a P&R perspective is that the FDSOI technology can use the conventional design flows and is completely transparent to the tools.

FinFET is another newfangled technology using 3D transistors that promises the sun and the moon in terms of power, performance and area. FinFET devices have their channels turned on their edge  with the gate wrapping around them. The term “fin” was coined by professors at Berkeley to define the thin silicon conducting channel. This unique configuration provides a gate that is wrapped  around the channel on all three sides thereby delivering much better channel control and better resistance to dopant fluctuations. Due to the innovative 3D structure and tighter channel control this technology delivers improved area better performance and lower power than bulk. P&R flows are expected to have minimum impact due to FinFET devices. FinFET technology is in production at 22nm and is quickly ramping up for the next generations.

FinFET with wrapped gate

Whether these two technologies will continue their battle to dominate or collaborate and co-exist successfully as we continue the march towards single digit micron devices remains to be seen. Once  thing is for certain – both these technologies will give a significant boost to the designers in terms of power reduction and performance. As always, production volumes with determine the eventual  winner. Just look at shamwow sales numbers if you don’t trust me.

FD-SOI, fin grid, dual gate, MugFET, Tri-gate, FinFET, full depleted SOI

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About Arvind Narayanan

Arvind NarayananArvind Narayanan is the Olympus-SoC product marketing manager for Mentor’s place and route group. Arvind started his career as a microprocessor design engineer for Hal Computer Systems and has been in the semiconductor industry for over 14 years in different capacities, ranging from processor design engineer to application engineer and product marketing. His EDA experience includes working on STA at Synopsys and low power design analysis and implementation at Magma. At Mentor he has a broad view of the latest low power design techniques being used at our most advanced customers. Arvind earned his MS in Electrical and Computer Engineering from Mississippi State University, and MBA from Duke University. Visit The Power Play

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