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David's DAC09 - Lunch & Learn

My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP.

It started with a rather unexpectedly good lunch. Usually, I don’t like the buffet like food you get at these things but this was both good and healthy. They had grilled vegetables, two different salads, Chicken, Halibut, and beef. I have been working on my cholesterol (Design for Maturation), so I stuck to the Halibut. However, after filling the belly we got down to business and each of us gave our own view of the partnership.

I, of course, focused on all the DFM tools we have developed over the last 4 years YieldAnalyzer, CMPAnalyzer, YieldEnhancer,  and LFD. The YieldAnalyzer tool supports two types of analysis. the first is Critical Area Analysis or CAA which analyzes the design sensitivity to random defects in the manufacturing process. The second is Critical Feature Analysis or CFA which analyzes the design sensitivity to the host of issues covered by recommended rules. CMPAnalyzer models the thickness variation and the YieldEnhancer tool provides several modes of fill to help improve the planarity. Finally, LFD or Litho Friendly Design, models the 2D variation due to litho/etch effects. However, my main point really was to say that all these tools were not much use without the partnership that provides the configuration data and use models that put them into useful practice. That is what was nice about having Rob Aitken from ARM and KK Lin from Chartered there to really show how they had enabled and utilized the tools to improve the DFM quality of incoming IP.

Rob talked about how ARM had learned over the history of cooperation since 90nm to get better and better at DFM. He also pointed out that it is very important for them to interact very early in the process development life cycle with Chartered to assure their IP is ready for customers when they need it. Their approach to making IP DFM compliant is to make it part of the architecture and design process as opposed to and add-on activity. I think that is a really smart way to go. I learned a lot from the following slide that showed the various DFM loops that ARM utilizes in improving their IP.

dfm-loops2

The first is the tightest loop where the designer is using the tools interactively to optimize the IP as it is designed. Once that is complete they do additional analysis on the whole library to look for outlier cells that need to be cleaned up. They then work with Chartered to have them analyze the cells for any fine tuning. Finally, everything is evaluated in silicon test chips to see if anything was missed. Many people only do the last long loop which is very expensive and does not lead to good DFM quality IP.

Rob had some great results data that showed both performance and yield gain due to these types of activities. The following slide shows the performance and yield metrics from 5 different  implementation appoaches of the same set of IP. In the chart the higher the value the better performance. The yield metric combines yield with cell utilization information to get a number in which the higher it is the better.

silicon-validation

As you can see approach 1 had high performance and high yield. Approach 4 had high performance but much lower yield. Approach 3 had poor performance and mediocre yield. This shows that different approaches to implementing IP and DFM can have significant impact on the final result.

KK talked about how they had continued to refine and expand their DFM offerings over the last 4 years and 4 technology nodes. This included not only configuration data for our DFM tools but also use flows and acceptance criteria development. The slide below shows their acceptance criteria flow for IP and the web portal that they allows customers to access that shows which IP has which level of qualification including DFM.

ip-website

I think that this type of process and information availability is really unique to Chartered. I know that I would want to know the quality status of IP I was going to use in a design. It is also great when someone else goes to the trouble to do the evaluation for you. KK also showed a great set of data about the DFM scores of the last three stdcell libraries that they qualified with ARM.

dfm-score-distributions

Each chart is a histogram of the DFM scores for a whole library of cells. The score ranges from 0 to 1 and the higher the better. The top chart are the scores for redundancy and the bottom is the scores for the process margin checks. You can see that all the cells from all three libraries have distributions highly biased to the right with a small std dev. The yellow distributions are from the most recent library that went through the most recent DFM processes and you can see that it is better than the previous generations. I just love to see people drive improvement with data instead of just talking about it. It always amazes me how creating metrics like this drives long term improvement.

Finally, KK showed some test chip results from a paper that Samsung (their alliance partner) presented at SPIE in February.

samsung-testchip-results

They ran a test chip with and without DFM enhancements alternating on the same wafer. The non-DFM version yielded 79% and the DFM version yielded 87%. That is 8 points in yield! The leakage and speed distributions were also better on the DFM version of the design. Finally some data to back up what everyone knows but wants to deny about DFM. It does make a difference!

Well that just goes to show that it is possible to have a good meal and learn some good information all at the same time:)

Design Quality, Design for Manufacturing, IP, Physical Verification, Yield

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About David Abercrombie

David AbercrombieI am the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last five years at Mentor I have been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. For the previous 15 years I drove yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. I also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. I hope you will read my publications and patents on semiconductor processing, yield enhancement and EDA verification solutions. I received my BSEE from Clemson University in 1987 and my MSEE from North Carolina State University in 1988. I love to play the guitar, explore the great outdoors, and watch a great science fiction show. Visit David Abercrombie’s Blog

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