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David's DAC09 - Off to a great start!

Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin and then headed to bed.

Monday began pretty early for me. I gave the 9am presentation in the Mentor suite on eqDRC (Equation-Based DRC). I say that I gave it but it turns out I had a great special guest who did most of the talking. Jim Culp (the “DFM Jedi” as we call him) at IBM in Fishkill, NY was on hand and agreed to present on the work he has been doing with the eqDRC capabilities at IBM. I gave a brief intro to the basic idea and concepts behind eqDRC and then let Jim run with it. Here is a not so professional picture of him doing the presentation. Sorry Jim:)

photo_072709_007_crop1

I have been amazed over the last 1-2 years what Jim has done. He has been one of the first guys to really grasp the potential power of the eqDRC capability and apply it to real world problems. He was only able to discuss the most mature of his ventures to date which was related to chip leakage analysis, but I know that he has several other applications he has done with it as well. Jim’s focus has been to use the generic tool capability as a platform for modeling circuit yield loss mechanisms on incoming designs into the foundry at IBM.

For the leakage application he set out to generate a much more accurate modeling capability of static chip leakage that can run in just a few hours and give the foundry and the designer much more information about what to expect in leakage and what issues they may not be aware of. Jim presented the graph below to explain why he thinks static leakage analysis is so important in advanced designs.

leakage-trend

The static leakage is becoming a dominant source of the total leakage and failure to predict it properly can cause significant yield loss in production when your leakage specs are tight.

The one thing people always bring up about eqDRC is “how do I get the equation”. Well Jim’s approach for leakage modeling was to use the SPICE models that the foundry provides to generate data for an empirical fit. For instance. Below is the equation form and example data fit that he used for the N-Well proximity effect on transistor leakage.

nwprox-equation-form

nwprox-calibration

Using this technique combined with using equations you can get from any device physics book, Jim was able to create a complete set of statistics on leakage for each transistor in the layout that is unique to its specific context. Below is a picture of how he is able to “grade” each transistor.

per-gate-leakage2

Once the leakage of each transistor is modeled Jim’s uses Calibre to statistically roll up the leakage into a “heat map” as shown below.

iddq-map

With this he can predict the total chip leakage and distribution across the wafer. He also uses this to compare with the actual heat map from the real chip in failure analysis. If there are mismatches between the model and the actual he can identify them to either understand a new mfg issue or better tune the model.

Each of the parameters that contribute to leakage are separately calculated and analyzed for distribution and outliers. The following is an example chip distribution of narrow channel effects (NCE).

nce-distribution

He stated that most designers assumed parameters like this had a normal distribution. Clearly this is not the case and there are some dramatic outliers to the distribution. These transistors can now be highlighted on the layout to determine what is causing them and hopefully to drive layout changes to fix them.

All in all, it was an amazing presentation and a great start to DAC!

IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

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About David Abercrombie

David AbercrombieI am the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last five years at Mentor I have been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. For the previous 15 years I drove yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. I also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. I hope you will read my publications and patents on semiconductor processing, yield enhancement and EDA verification solutions. I received my BSEE from Clemson University in 1987 and my MSEE from North Carolina State University in 1988. I love to play the guitar, explore the great outdoors, and watch a great science fiction show. Visit David Abercrombie’s Blog

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