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David's DAC09 - White Paper Session

I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. The paper was part of track 5 on Tuesday at DAC. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor Pikus, the Lead Software Architect, and Cosmin Cazan, a Portland State University Intern, on this project.

If you don’t already know, eqDRC is just a set of command extensions we have added to the base Calibre DRC product that enables new ways to define and implement design rule and recommended rule checks. Basically, it enables a simple mathematical modeling engine based on multi-dimensional geometriclayout measurements. That is a fancy way of saying that DRC is no longer limited to overly simplistic one dimensional measurements to determine if a layout is manufacturable. It allows defining equations that relate multiple dimension measurements together. With eqDRC you can better approximate the physics of the manufacturing issue or at least a much more accurate empirical model of the phenomenon. Here is a link to some papers and on-line seminars on the subject:

One of the questions that everyone always brings up is “how do I determine the equation?”. Well there are many answers to that and it also depends on who you are. If you are the fab engineer who defines the design rules normally, then you either have silicon wafer data where you have characterized the phenomenon or you are pulling the rule out of your @#$ based on your experience. Either way, I would argue that it is just as easy to define a mathematical function for the phenomenon as it is to pick some points along the curve to make a bunch of “bucketed” single dimensional rules. If you are in the fabless design house and you are defining design methodology checks then you know the phenomenon you are trying to check. Look to see if a mathematical relationship would capture the rule intent better than a bunch of single dimensional checks.

The challenge is when you are a fab guy without silicon data or a fabless guy trying to build a better check for a fab issue. A good example of this is litho corner rounding. Everyone knows that these days layout is not WYSIWYG. The picture below shows how the as manufactured poly shape diverges from the drawn causing potential changes to the effective gate channel length near the active edge.


Today most of us check this kind of phenomenon with a simple spacing check between the bent poly and the active. You can easily see that this does not accurate model such a complex situation. This is the reason we have built process simulation tools like Litho Friendly Design (LFD) to accurately simulate the image contours. The advantage of solutions like LFD is that the foundries provide the configuration data kits for a fabless company to use to do their own simulations. The disadvantage to these tools is that the simulation is much more compute intensive than standard DRC deterring the use in a iterative loop during layout. In this paper, we proposed a flow combines advantages from eqDRC and LFD. We started by defining a two dimensional empirical model for this phenomemon as shown in the next picture.


We found that combining the width (distance from the l-poly to active) and the run length (length of the poly bend) gave good results vs simulation. Intuitively, the rounding effect changes exponentially with width and linearly with run length. We then drew a bunch of simple GDSII test structures in which we varied the width and run length and ran the LFD simulator on them to see how the actual contours varied from drawn at the gate edge. Below is a picture of the test structures and the data we extracted.


This data is simple and fast to run with the simlator because the GDSII is so small. We curve fit this data using Microsoft Excel using the model form shown earlier and calibrated an equation we could code in Calibre nmDRC using the eqDRC functionality. For each gate we summed the corner rounding effect from each side of the gate to get the total gate length variation. We then ran both the eqDRC and LFD solutions on a real design and below is a comparison of the results from each.


You can see that there is very good correlation between the empirical equation method and the simulation method. The advantage is in run time. On a big design like this the simulation can run for days and the eqDRC deck can run in minutes. The results can be graded by how much gate length variation as shown in the following picture.


The full flow for utilizing the best of both tools is shown below.


You use the LFD simulator to calibrate an eqDRC deck. You then use the eqDRC deck in the iterative layout loop when you are trying to optimize your layout. You then use the eqDRC deck to define the most sensitive locations in your layout after you have finished optimization. Finally, you run LFD on these limited sites to get a high resolution accurate simulation to make sure nothing is still out of spec. These last two steps help improve the run time of the simulation on the whole layout by limiting where it needs to run.

Overall, I really think this shows a practical use of tools you can get from us and data you can get from your foundry to make a very useful flow for analyzing and optimizing a very complex manufacturing issue in your layouts. The only challenge at DAC was that I had to present the whole thing in 15 minutes! Luckily I talk fast. I would love to hear your feedback on this approach or ideas you might have to apply this concept to other issues.

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

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About David Abercrombie

David AbercrombieI am the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last five years at Mentor I have been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. For the previous 15 years I drove yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. I also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. I hope you will read my publications and patents on semiconductor processing, yield enhancement and EDA verification solutions. I received my BSEE from Clemson University in 1987 and my MSEE from North Carolina State University in 1988. I love to play the guitar, explore the great outdoors, and watch a great science fiction show. Visit David Abercrombie’s Blog

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