DFM for Non-PhDs
DFM for Non-PhDs
I got a kick out of Rohan’s comment on my previous blog (How do you define DFM?). It is too easy to assume that anyone knows what you are talking about when you say DFM. Just because everyone has been talking about it doesn’t mean any of them know what they are talking about.
You could probably infer from my approach to the previous blog that my background is primarily on the manufacturing side. I was responsible for yield and reliability improvement in the wafer fab. We measured yield and reliability by counting the difference between the total number of die (chips) that we started at the beginning of the manufacturing process vs the number of die that passed a series of electrical and physical tests at the end of the process. You can measure this as a percentage, but this is misleading because different designs have different die sizes which builds in a bias towards large die sizes yielding lower. It is simply a matter that big die have more surface area and circuit content so they have a higher chance of getting impacted by any particular issue than a small die. Because of this issue, a metric called Defect Density (Dd or D0) is used to normalize yield across different die sizes. The chart below shows the expected yield by die size for a specified Dd. For a given die size you can predict the percent yield assuming a exposure to a constant fab defect rate.
This Dd provides a very simple single measurement to track yield across product lines. It also provides a convenient hammer for management to beat you with:) However, making the numbers get better is a whole different ball game. With hundreds of process steps from beginning to end, it is like chasing cats trying to tune out and control all the variation. That is why we were so focused on measuring data at every step along the way.
The thing that ultimately led to my transition into EDA was that we began to notice that some designs didn’t follow this curve. In the following chart you can see some of the data from my previous life in which we plotted a wide assortment of our designs on this curve. Each point on the chart represents the yield for a given “lot” of wafers (25 wafers) run through the fab.
You can see in the chart that products 1,2 & 3 have very similar die sizes but dramatically different average yields compared to each other even though they were running on the same process in the same fab at the same time. They yield consistently but differently. Clearly, something was fundamentally different between them that make product 3 much more sensitive to the fab issues than product 2. Also note product 7. It yielded very inconsistently from lot to lot. In other words, slight variation differences from one process run to the next would have dramatic effects on its yield. You can’t blame these problems on the fab because they all got the same process and the other products fit the curve as they should.
The take away for the non-PhD is that design can make a difference on yield and just passing DRC, LVS & timing does not account for this difference . The trick is figuring out what variations in design lead to these variations and determining ways of eliminating these variations. The process, tools and methods for doing this are DFM. In my next blogs I will discuss how this manifest itself in reliability problems as well and the various types of design variations that cause these issues.
More Blog Posts
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- On-line session covering the DAC presentation for Calibre xACT 3D
- You can't give stuff away fast enough
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
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- June, 2010
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- April, 2010
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- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
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