If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives.
Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation less uniform, and thinner dies reduce the heat spreading capability of the die, creating greater on-die temperature variation.
Chip-package thermal co-design is particularly important when designing stacked three-dimensional integrated circuits (3DICs). The dies cannot be designed independently due to their electrical and thermal interaction.
If you need to understand the why, when, and how of thermal co-design, you need to read our new white paper, “7 Key Considerations for Effective Chip-Package Thermal Co-Design…A High-Level ‘How to’ Guide.” With detailed explanations of each step, it provides a clear roadmap through the process, and helps you avoid common mistakes and pitfalls along the way.
Don’t let global warming destroy your next SoC design!