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How do you debug LVS?

There are many way to skin a cat, so the saying goes… (well, at least in English… I’m sure each nationality / language has something similar). So when your debugging and verifying your IC design with LVS, what information do you use? Are you a text report kind of engineer, pouring over the text files that Calibre LVS generates? Are you an RVE wiz, preferring to do things in a GUI? Or do you use a bit of both, or something else? I’m sure there are also a number of custom GUIs that have been internally developed.

With the 2009.2 version of Calibre, we launched a new version of RVE, our GUI based results viewing environment for Calibre. This is an exciting new release with a number of significant enhancements tuned specifically for LVS. Some of these include schematics generated from the source and extracted netlists (great if you have a no schematic, like Verilog only), improvements to short isolation and a new report option, LVS REPORT OPTION FX. If you haven’t seen RVE for a while, now might be a good time to give it another look.

While final verification needs to happen in the Calibre version specified by your foundry, getting to LVS Clean does not have to. Why don’t you give 2009.2 or later a try and see how the New RVE and new FX report option goes for you…

Have you already tried it? Let me know what you think… Anything you’d like to see in there? Well, let me know that too…



Debugging, RVE, LVS

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About Matthew Hogan

Matthew HoganMatthew Hogan is a Calibre Marketing Engineer for Mentor Graphics. With over 15 years of design and field experience, he is well-versed in the issues that are imposed on today's aggressive designs. Matthew holds a B.Eng and an MBA. Visit Matthew Hogan's Blog

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