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IBM Addresses Leakage

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield loss in advanced technology nodes.

One of his areas of focus has been static chip leakage. He showed how the static leakage has become a significant if not dominant contributor to total leakage. Estimating chip leakage during design has historically been a “back of the envelop” calculation using some form of device count, maybe L&W counts and a bit of excel magic. Jim asserts that this is no longer sufficient to protect against a profit impacting “surprise” when the chip hits production. He was determined to find a better way.

Jim had attended a presentation I gave a long time ago on equation-based DRC and how we were trying to add functionality to the traditional DRC language to enable a new approach to checking. He quickly grasped that this capability might give him the tools he needed to attack this leakage prediction problem. He developed empirical equations to model the various components of device leakage, calibrated them using the SPICE decks from the fab and coded them in Calibre nmDRC.

Not only did he get better prediction accuracy, but he was able to get much improved visualization and drill down into the contributions and prioritization of the gates with them most problem. They use the tool in a complete flow to identify problem designs early, validate results as the chips move through production and improve the model over time by localizing discrepancies between the model vs actual and improve the equations.

Unfortunately, we were not able to record the webinar, but Jim has been gracious enough to allow us to make the slides available for you to see. Here is a link to them: slides. I hope that you find them as intriguing and inspiring as I did.



Physical Verification, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

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About David Abercrombie

David AbercrombieI am the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last five years at Mentor I have been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. For the previous 15 years I drove yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. I also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. I hope you will read my publications and patents on semiconductor processing, yield enhancement and EDA verification solutions. I received my BSEE from Clemson University in 1987 and my MSEE from North Carolina State University in 1988. I love to play the guitar, explore the great outdoors, and watch a great science fiction show. Visit David Abercrombie’s Blog

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