When I was at PDF Solutions we launched a campaign that stated DFM is now the designer’s problem. It was not a resounding success as at 90nm, the majority of designers simply stated, “No it isn’t—it’s the fabs problem.”
While DFM was evolving and the major wrinkles were being ironed out, designers enjoyed a “grace period” when the dangers of not doing DFM checks were perhaps overstated, and the practical reality of who was responsible was at best shared. But realistically, it was the fab’s responsibility unless proven otherwise.
Now major foundries have essentially served notice to the industry—the implied contract between the foundries and their fabless customers is changing, and DFM is now the designer’s responsibility. This applies not only to SoC designers, but to IP design teams as well.
Foundries are indicating in their various ways that the responsibility for doing DFM checks, and making sure a design is optimized for manufacturing, lies with the designer. TSMC has been doing education seminars with Mentor on DFM and has made model-based litho and CMP checks mandatory at the 45/40nm node, with CAA checks highly recommended. Chartered Semiconductor, working with ARM and Mentor Graphics, has developed a methodology for DFM scoring of IP, and has made DFM scoring a requirement for IP that will be purchased by the Common Platform at 32nm. SMIC is making DFM checking a requirement at 65nm and below for all three DFM functions litho, CMP, and CAA.
At the Mentor-TSMC DFM seminars there were multiple questions from the attendees about what “mandatory” truly meant, arguing the fine points of one scenario vs. another. What the audience was not grasping was that the implied contract has changed from “if there is a yield problem after DRC signoff, it’s the fabs fault” to “unless you have data verifying a DFM-clean design, it’s the designer’s fault until proven otherwise.”
The nature of the customer-supplier relationship is such that the foundries are reluctant to force new requirements, that admittedly have associated cost and time impacts, on their customers. However, they are being very clear that if a customer chooses not to run the recommended DFM checks, and yield problems surface during first silicon or later, the burden of proof will be on the foundry’s customer to show that the design is DFM clean.
So, like it or not, if you’re moving to the most advanced process nodes, start thinking about DFM the way you are used to thinking about DRC.
For more on this topic, see Simon Favre’s blog post, “What Do You Mean by Mandatory?” at http://www.mentor.com/products/ic_nanometer_design/blog/post/what-do-you-mean-by-mandatory–5d73a87b-729d-4e52-bf90-90844ee96189