Are you a TSMC customer or partner? If so, you’ll want to take a look at our presentations from the 2013 TSMC Open Innovation Platform conference.
Design Reliability with Calibre YieldEnhancer/SmartFill and Calibre PERC
Broadcom & Mentor Graphics
The complexity of advanced technologies drives new requirements for poly/OD and metal fill to solve critical manufacturing effects, and more importantly design yields. Tighter geometries also require new and more complex electrical rule checks to ensure high reliability. Both Calibre SmartFill and Calibre PERC were successfully deployed on Broadcom’s largest 28nm tapeout, enabling Broadcom to meet strict new DFM requirements and validate high reliability design metrics while reducing runtime, file size, and iterations.
Through close cooperation between Mentor and Synopsys, Synopsys Laker users can now check with Calibre “on the fly” during design to speed creation of design-rule correct layout, including electrically-aware voltage-dependent DRC checks.
Verify TSMC 20nm Reliability Using Calibre PERC
As semiconductor technology aggressively advances past Moore’s Law, various reliability issues have arisen due to geometry shrink and the increase of electrical stress. Mentor presents Calibre PERC, a tool platform that is fully qualified for the verification of rules defined in TSMC N20 DRM for TDDB of inter-metal dielectric and CDM ESD reliability issues.
EDA-Based DFT for 3D-IC Applications
Testing of TSMC’s 2.5D/3D ICs implies slight changes to traditional Built-In Self-Test (BIST) insertion flows provided by commercial EDA tools. Mentor discusses the changes made to test tools and methodologies to ensure accurate and full testing of these devices, reducing expensive design iterations or ECOs and ultimately translating to a lower cost per device.
Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC
Mentor Graphics & nVIDIA
Top-level chip assembly and optimization is a highly iterative and manual process that can have a huge impact on design turn-around time and QoR. Mentor and nVidia discuss the chip assembly and design closure solution for TSMC processes, including concurrent MCMM optimization, synchronous handling of replicated partitions and layer promotion of critical nets for addressing variation in resistance across layers.