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Mixed-Signal SoC Verification

Karen Chow

Karen Chow

Posted Jun 17, 2009

More and more digital processing functions isolated into multiple power domains, hundreds or thousands of analog-digital interconnections, operating frequencies always closer to pure RF — clearly, genuine full-chip verification of complex mixed-signal systems-on-chip (SoCs) calls for careful planning and organization, as well as flexible simulation technologies. Whether you are verifying a power-management circuit, a single-chip multi-standard radio transceiver, or a mobile communications processor, different strategies are required. Technologies that allow transparent and efficient combinations of analog/RF descriptions, analog/mixed signal (AMS) behavioral models, and pure digital descriptions — all interoperating under a common verification platform — can help maximize full-chip, mixed-signal verification.

Mixed signal design starts are increasing. An AMS SoC designer applies various design formats for the different blocks, with different levels of abstraction. The different formats are typically classified into either digital or analog design.  For purely digital designs, many production-proven tools are available for standard cell creation, behavioral language simulation, synthesis, and place and route. For analog designs, traditional tools are used for schematic entry, accurate device-level simulation, handcrafted layout, and interactive wiring.

How do you integrate the design blocks at the chip level and complete the testing and verification? Do the blocks really fit together at the top level? Will the design function as planned? To ensure a working design, an AMS/SoC chip-level design needs to be verified in its entirety. For this purpose, digital/analog (D/A) integration is mandatory. Shrinking manufacturing processes require inclusion of parasitics for analysis, and the integration of parasitic data adds yet another level of complexity to this problem. However, a post-layout simulation netlist can be created that includes parasitics and handles various data formats and that will effectively re-simulate the design using layout parasitic effects to maintain signal integrity.

Yield problems and multiple spins are caused by missed deep submicron effects. Mixed-signal SoC designs require full-chip timing analysis as well as full-chip signal integrity analysis. Unfortunately, flat full-chip parasitic netlists are huge and impossible to simulate with traditional flat SPICE-type simulators.

How do you deal with these issues?

Mixed-Signal, IC Design

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About Karen Chow

Karen ChowKaren Chow is the Technical Marketing Engineer for Calibre xRC and Calibre xACT 3D at Mentor Graphics in Wilsonville, OR. She has worked on both sides of the EDA industry, designing analog ICs and supporting EDA tool development. For the past six years, she has been focusing on driving parasitic extraction development in analog and RF design flows. She has also worked as a senior applications engineer for Mentor Graphics in Ottawa, Canada. Prior to Mentor Graphics, she worked at Nortel Networks in Ottawa, Canada, focusing on synchronization for optical switches and analog IC design for telephony applications. Karen has her BSc in electrical engineering from the University of Calgary, and her MBA from Marylhurst University. In her spare time, she enjoys playing music in bands, designing clothing and handbags, and quilting. Visit Karen Chow's Calibre Blog

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Comments 3

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Karen, You mentioned "traditional flat SPICE" in this blog. Whatever happened to the simulator integration between the hierarchical HSIM and Advance MS? That combination should allow a designer to simulate a full-chip at the SPICE and HDL levels.

Daniel Payne
8:04 PM Jun 18, 2009

I haven't seen much adoption of HSIM with Advance MS, but have seen more of Advance MS with Adit. It's now called Questa ADMS.

Karen Chow
6:13 PM Jun 19, 2009

Thanks for the udpate.

Daniel Payne
10:20 PM Jun 25, 2009

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