More and more digital processing functions isolated into multiple power domains, hundreds or thousands of analog-digital interconnections, operating frequencies always closer to pure RF — clearly, genuine full-chip verification of complex mixed-signal systems-on-chip (SoCs) calls for careful planning and organization, as well as flexible simulation technologies. Whether you are verifying a power-management circuit, a single-chip multi-standard radio transceiver, or a mobile communications processor, different strategies are required. Technologies that allow transparent and efficient combinations of analog/RF descriptions, analog/mixed signal (AMS) behavioral models, and pure digital descriptions — all interoperating under a common verification platform — can help maximize full-chip, mixed-signal verification.
Mixed signal design starts are increasing. An AMS SoC designer applies various design formats for the different blocks, with different levels of abstraction. The different formats are typically classified into either digital or analog design. For purely digital designs, many production-proven tools are available for standard cell creation, behavioral language simulation, synthesis, and place and route. For analog designs, traditional tools are used for schematic entry, accurate device-level simulation, handcrafted layout, and interactive wiring.
How do you integrate the design blocks at the chip level and complete the testing and verification? Do the blocks really fit together at the top level? Will the design function as planned? To ensure a working design, an AMS/SoC chip-level design needs to be verified in its entirety. For this purpose, digital/analog (D/A) integration is mandatory. Shrinking manufacturing processes require inclusion of parasitics for analysis, and the integration of parasitic data adds yet another level of complexity to this problem. However, a post-layout simulation netlist can be created that includes parasitics and handles various data formats and that will effectively re-simulate the design using layout parasitic effects to maintain signal integrity.
Yield problems and multiple spins are caused by missed deep submicron effects. Mixed-signal SoC designs require full-chip timing analysis as well as full-chip signal integrity analysis. Unfortunately, flat full-chip parasitic netlists are huge and impossible to simulate with traditional flat SPICE-type simulators.
How do you deal with these issues?