Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very complex to write, slower to run and increasing difficult to debug. Pattern matching has the potential to be a game changer by simplifying advanced checks, making it easier to develop/maintain them, produce smaller DRC decks that run faster, and make debug simpler: maybe not a complete solution for world hunger but certainly is a real win for today’s IC designer – enabling the designer to go from a dirty design to tape-out faster.
Why is DRC Becoming So Hard?
In a nutshell, because the IC lithography industry has not delivered resolution improvements as fast as Moore’s law has shrunk design geometries, the EDA industry must now provide a larger fraction of the resolution improvement. As ICs shrink, the range over which lithographic and electromechanical interactions occur expands in proportion to the size of individual physical features. In addition, with wafer steppers stuck with 193nm light sources, the distortions due to diffraction effects result in more numerous and subtle design-for-manufacturing issues. This makes design rules increasingly complex. Initially simple 1-D spacing, length and width measurements between immediately adjacent features (transistors or interconnect wires), IC design rules must now take into account many more complex, 2-D geometric measurements, and combined groups of measurements related by complex functions, in order to determine if a design is manufacturable at advanced process nodes.
As a result, DRC is becoming exponentially more difficult to define and execute, which has many real-world implications for IC design and process engineers who have limited time and headcount, and IC executives who need to get advanced products to market quickly with high yield to stay competitive. Across industry, the number of DRC checks is growing at more than 20% node over node. Even more alarmingly, the number of individual operations required to execute each check is also growing—at more than 30% node over node. This explosion in size and complexity increases the difficulty of creating DRC decks, causes longer PV run times, and requires more time to debug DRC violations. The bottom line is that the current trend increases the time needed to achieve physical implementation closure.
Reversing the “Runaway DRC” Trend
How can we reverse the trend and maintain the PV cycle times required to remain competitive and drive industry growth? To get a perspective on a possible solution, consider that much of PV is really based on a simple concept: certain geometric shapes (from the perspective of a layout representing IC lithography masks) cannot be manufactured with a given process. Therefore, we can’t let designs use these shapes.
Today when the failure analysis (FA) group determines a geometric configuration that cannot be manufactured, they write a specification for a new design rule. The new rule is then passed on to a different person who needs to interpret the rule and write a new DRC check using the PV scripting language, trying to accurately represent the original pattern and design rule. Some pattern configurations or variants of a single configuration are so complex they simply cannot be accurately (or practically) described with existing scripting languages, and errors in the checking process are the inevitable result. A lot of time and energy is expended trying to get congruence between the original intent of the design rule, and its implementation as a design rule check defined in the PV tool.
How Pattern Matching Might Solve World Hunger
Imagine if you could use the original problematic pattern found by manufacturing to define the DRC’s, you dramatically simplify the communication of the problem from manufacturing to the designer, and you are now using a language (i.e. geometric pictures) that everyone can understand. By using visual patterns for the DRC’s you avoid having to convert the design rules into an abstraction in the scripting syntax.
This is the concept of pattern matching for PV. Instead of using a scripting language to describe the relationship between geometries in a design, create and use a library of patterns. An IC design is then scanned using this library of patterns to find matches. Once a match is found an error marker is produced at the site of the match.
The library of patterns can be either hand drawn or created with the aid of EDA tools such as a pattern matching GUI environment where the user can create new patterns, specify edge constraints and manage their pattern library. The pattern matching GUI could also use an existing layout with error markers from a prior run to automatically clip patterns to create or add to a library.
The Impact of Pattern Matching
Where historic 1-D DRC checks might have been written in one or two operations today’s 2-D checks takes tens if not hundreds of lines. Many of these enormously complex checks are simply trying to describe 2-D patterns using syntax originally architected for doing 1-D checks. These advanced checks could be collapsed from tens to hundreds of operations down to one operation pointing to a pattern. This alone could dramatically slow the explosion in DRC deck size and complexity. Smaller, simpler DRC decks are easier/quicker to create and maintain. Smaller DRC decks run faster. Simpler DRC checks are easier for your designer to debug. The whole physical verification process gets simpler and moves faster getting your design to market faster.
Pattern matching will not immediately replace traditional DRC but will provide a powerful tool to simplify the most complex checks. Pattern matching may not quite solve world hunger but it does offer the promise of reversing the runaway DRC trend by providing an alternate, and far simpler, method of dealing with the most complex new checks required for advanced IC processes.