Source Netlist Creation for LVS

Source Netlist Creation for LVS

Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future…

Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout is good. The actual proof of comparing two dis-similar, yet equivalent SPICE netlists is handled pretty well by layout versus schematic (LVS) tools. Over the years a nice solid methodology for this comparison has been developed and the mechanics of LVS are well understood by many. But getting to the point where you have that trusted source netlist to take to comparison still seems as much experience and art, as it is about the technology. Especially for a complex mixed-signal design. A good dose of faith in your process, trust in your LVS tool, and experience to tie it all together seem to be a common (and winning) strategy that many often use.

So, how do you go about managing the complexities of putting together your trusted source netlist? Single language designs from SPICE or Verilog may seem easy enough, at least conceptually, while mixed-signal designs require a bit more fiddling - So how do you know your done? In Calibre land, there are some utilities to aide with the transformation. Do they suffice? Or are you using something internal, or looking for more?

Let me know your thoughts and opinions…

Matt.

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