TSMC 28nm yield (SemiWiki)

TSMC 28nm yield (SemiWiki)

I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield:

“I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, or many measurements of test structures. The fact is, one design can yield differently from another purely due to defect limited yield. That’s what critical area analysis is for. Design teams that do critical area analysis and take corrective action tend not to have defect or process limited yield issues. They actively reduce the sensitivity of their design to random defects. A design that has a high sensitivity to random defects will yield poorly on the same process, where a design properly tuned for critical area will yield better. In that sense, a high sensitivity to random defects is a design-limited yield issue, or a design-induced yield issue. The thing is, unless the companies that have poor yields publicly discuss the sources of yield loss, whether due to OCV, power density, voltage drop, random defects, or any of a host of other causes, the industry as a whole will not gain anything from this painful learning they went through. ”

Main SemiWiki article:

http://www.semiwiki.com/forum/content/1054-tsmc-28nm-yield.html

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