- Design Reliability with Calibre YE-SmartFill and Calibre PERC (Broadcom & Mentor Graphics)
New methodologies were developed for 28nm designs using Calibre SmartFill and Calibre PERC. Calibre SmartFill was deployed to meet the new strict DFM requirements while reducing run time, file size and iterations. Design consistency checks written with rules in Calibre PERC were implemented to catch design mistakes early in the design flow process, and validate high reliability design metrics.
- Synopsys Laker Custom Layout and Calibre Interfaces: Putting Calibre Confidence in Your Custom Design Flow (Mentor Graphics)
Through close cooperation between Mentor and Synopsys, Synopsys Laker users can check with Calibre “on the fly” during design to speed creation of design-rule correct layout, including electrically-aware voltage-dependent DRC checks.
- Verify TSMC 20nm Reliability Using Calibre PERC (Mentor Graphics)
Calibre PERC was used in close collaboration with TSMC IO/ESD team to develop an automatic verification kit to verify CDM ESD issues for the N20 node.
- EDA-Based DFT for 3D-IC Applications (Mentor Graphics)
Testing of TSMC’s 2.5D/3D ICs implies changes to traditional Built-In Self-Test (BIST) insertion flows provided by commercial EDA tools. Tessent tools provide a number of capabilities that address these requirements while reducing expensive design iterations or ECOs, which ultimately translates to a lower cost per device.
- Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & NVIDIA)
Mentor and NVIDIA discuss the chip assembly and design closure solution for TSMC processes, including concurrent MCMM optimization, synchronous handling of replicated partitions, and layer promotion of critical nets for addressing variation in resistance across layers.
TSMC OIP presentations now available!
More Blog Posts
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- TSMC OIP presentations now available!
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- March, 2014
- February, 2014
- January, 2014
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- July, 2013
- April, 2013
- March, 2013
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
- August, 2010
- June, 2010
- May, 2010
- April, 2010
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
- Calibre Everywhere -- the customer value of universal integration
- So, why not just write better rules?
- To be the man, you've gotta beat the man!
- Power in need, Power indeed
- May, 2009