Mentor Graphics is excited to announce the launch of their new fast field solver for IC design, Calibre xACT 3D http://www.mentor.com/calibre-xact. This new tool is based Mentor Graphics’ acquisition of Pextra Corporation last year. This deterministic field solver has break-through performance, and excellent scalability, which enables the efficient use of multiple CPUs to achieve the fast turn-around-time. … Read More
In my last few posts, I began discussing on what it takes to enable software quality and support. This particular post will focus on the latter, support.
Of course the goal of any descent software provider is to deliver software that is bug free, intuitive to use, and performs a valuable service. While we strive for perfection, in reality these goals can never be fully achieved. In the EDA world, … Read More
Mentor Graphics, Physical Verification, Calibre, Quality, Support
This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More
Redundancy, CAA, SoC, SRAM
If attendance at the TSMC Technology Symposium in San Jose (link redirects) is any indicator, the economy must be improving. Official attendance was said to be 1500, but it felt like it was more. Of course, there were a lot of TSMC staff milling about, and they did have 2 of the booths in the vendor area for their own offerings, but there were still a lot of people there. The thing EDA vendors like … Read More
In both my last post, and in John Ferguson’s posts, the reasons, challenges and costs associated with “waivers” for DRC were discussed. As we have both pointed out, this is a growing problem as the IC industry increases its use of 3rd party IP while simultaneously the number of waivers within that IP is also increasing – resulting in a sea of waivers to deal with.
As we have deployed our Calibre … Read More
Waiver, Fab-lite, Fabless, Calibre, IC Design, Physical Verification, Foundries, Foundry
The recent earthquake in Taiwan did have an impact on TSMC’s production, but probably not as great as some in the press have indicated: TSMC loses 40K wafers in quake. This blog gives a more careful reading of the announcement. What it comes down to is “1.5 days loss of wafer movement for the company in total.”
Regardless of whether or not they had to scrap any wafers, 1.5 days of downtime is 1.5 … Read More
In my last blog I discussed the importance of support and the value it provides in the physical verification space. As indicated, one of the key components in providing support is having an infrastructure helps to assure quality software releases in the first place. In this blog, I will provide more insight into the procedures in place within the Calibre organization that help to ensure the high standards … Read More
Step 0 Commitment – Are you really sure you want to MV? Are you positive that Multi-Vt & Clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.
Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done … Read More
Isolation Cells, Level Shifter, Always on Buffers, Power Switches, UPF, MTCMOS, Multi-Voltage
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
IDM, IC Design, Pattern Matching, SoC, eqDRC, Calibre, Fabless, Physical Verification, Productivity, Foundries, Equation-Based DRC, PV, Sign-off, Fab-lite
When asked about the value that the Calibre platform brings to the design community, most folks will respond with performance, foundry support, and ease of debugging. While these are all valuable aspects and traits of Calibre, there is one more benefit that is often taken for granted: support.
The word “support” is something bandied around loosely in EDA. Saying you have good support is akin to saying … Read More
DRC, EDA Ssoftware Support, Calibre, LVS, Physical Verification
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC
Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers.
Why Do Competing PV Products Want to Use Calibre SVRF?
Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More
Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, DRC, Sign-off, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC
I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight.
Tezzaron Semiconductor … Read More
Deepchip, DRC, Calibre, Quartz, Tezzaron, LVS, Physical Verification
Clock designers are an enigma. Clock designers in general are die hard star wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in peak summer and have likeminded clock designers as best lunch buddies. Clock designers are notorious for making other lesser designers cry with their fancy PLL spice runs, non-negotiable … Read More
In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More
Physical Verification, Yield, Design Quality, Design for Manufacturing, IC Verification, Leakage, DRC, IC Design