Posted Jun 2, 2010, by John Ferguson
In my last few posts, I began discussing on what it takes to enable software quality and support. This particular post will focus on the latter, support.
Of course the goal of any descent software provider is to deliver software that is bug free, intuitive to use, and performs a valuable service. While we strive for perfection, in reality these goals can never be fully achieved. In the EDA world, … Read More
Tags:
Mentor Graphics,
Physical Verification,
Calibre,
Quality,
Support
Posted May 11, 2010, by Simon Favre
This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More
Tags:
Redundancy,
CAA,
SoC,
SRAM
Posted Apr 15, 2010, by Simon Favre
If attendance at the TSMC Technology Symposium in San Jose (link redirects) is any indicator, the economy must be improving. Official attendance was said to be 1500, but it felt like it was more. Of course, there were a lot of TSMC staff milling about, and they did have 2 of the booths in the vendor area for their own offerings, but there were still a lot of people there. The thing EDA vendors like … Read More
Tags:
EDA,
Economy
Posted Mar 30, 2010, by Michael White
In both my last post, and in John Ferguson’s posts, the reasons, challenges and costs associated with “waivers” for DRC were discussed. As we have both pointed out, this is a growing problem as the IC industry increases its use of 3rd party IP while simultaneously the number of waivers within that IP is also increasing – resulting in a sea of waivers to deal with.
As we have deployed our Calibre … Read More
Tags:
Waiver,
Fab-lite,
Fabless,
Calibre,
IC Design,
Physical Verification,
Foundries,
Foundry
Posted Mar 18, 2010, by Simon Favre
The recent earthquake in Taiwan did have an impact on TSMC’s production, but probably not as great as some in the press have indicated: TSMC loses 40K wafers in quake. This blog gives a more careful reading of the announcement. What it comes down to is “1.5 days loss of wafer movement for the company in total.”
Regardless of whether or not they had to scrap any wafers, 1.5 days of downtime is 1.5 … Read More
Tags:
earthquake
Posted Mar 15, 2010, by John Ferguson
In my last blog I discussed the importance of support and the value it provides in the physical verification space. As indicated, one of the key components in providing support is having an infrastructure helps to assure quality software releases in the first place. In this blog, I will provide more insight into the procedures in place within the Calibre organization that help to ensure the high standards … Read More
Tags:
DRC,
Mentor,
Calibre,
Quality,
Physical Verificaiton,
PV
Posted Feb 4, 2010, by Arvind Narayanan
Step 0 Commitment – Are you really sure you want to MV? Are you positive that Multi-Vt & Clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.
Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done … Read More
Tags:
Isolation Cells,
Level Shifter,
Always on Buffers,
Power Switches,
UPF,
MTCMOS,
Multi-Voltage
Posted Jan 28, 2010, by Michael White
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
Tags:
IDM,
IC Design,
Pattern Matching,
EDA,
SoC,
eqDRC,
Calibre,
Fabless,
Physical Verification,
Productivity,
Foundries,
Equation-Based DRC,
PV,
Sign-off,
Fab-lite
Posted Jan 27, 2010, by John Ferguson
When asked about the value that the Calibre platform brings to the design community, most folks will respond with performance, foundry support, and ease of debugging. While these are all valuable aspects and traits of Calibre, there is one more benefit that is often taken for granted: support.
The word “support” is something bandied around loosely in EDA. Saying you have good support is akin to saying … Read More
Tags:
DRC,
EDA Ssoftware Support,
Calibre,
LVS,
Physical Verification
Posted Jan 15, 2010, by Michael White
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags:
Foundry,
Foundries,
IC Design,
DRC,
SVRF,
EDA,
Tax,
Waiver,
Calibre,
Physical Verification,
Fab-lite,
Productivity,
Fabless,
Sign-off,
eqDRC,
SoC,
Equation-Based DRC
