Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More
IC Design Blog
The need for high reliability covers a wide array of market segments, all with differing acceptance requirements. In this video, Matt Hogan explores the challenges of comprehensive reliability verification, and demonstrates how Calibre PERC can help you satisfy the most demanding requirements with confidence. … Read More
No one wants to edit a foundry rule deck—it’s like tugging on Superman’s cape. But there are many ways to customize the input to a Calibre job without modifying the foundry rule deck. To learn more, watch one of our short, to-the-point How-To videos on our IC Nanometer Design channel on YouTube. Oh, and if you can’t find what you’re looking for? Suggest a new topic! … Read More
Personal GPS systems were a blessing for directionally-challenged people. Model-based hinting (MBH) for LFD hotspot corrections evoke a similar feeling of relief in engineers who are tired of late-night stints trying to figure out how to correct a litho hotspot without creating even more problems. MBH can evaluate your fix options and identify which ones are viable, helping you make better decisions … Read More
No Fear of FinFET FinFETs, or so-called 3D transistors, are a key competitive element in all the leading-edge IC foundry offerings, because FinFETs can achieve much lower power operation than planar transistors. This panel discusses how FinFETs will change the design, verification, and test flow. Panelists Joe Sawicki, VP and General Manager of the Design to Silicon Division, Mentor Graphics KK Lin, … Read More
At the recent TSMC OIP, I had an interesting discussion with a TSMC employee (who shall remain nameless), regarding 450mm wafers. The gist of the discussion was that EUV has become a gating item for the move to 450mm wafers. Why are these two related? They are connected at the purse strings. It will cost billions (with a B) to build a 450mm wafer fab. It will cost billions to go to EUV. Why pay this … Read More
I’ve just taken over editorial responsibilities for the Foundry Solutions content, and I look forward to bringing you the information and guidance you need to deliver innovative and profitable designs to the market. Our job and our goal is to help you get to tapeout on time, with confidence! Please feel free to suggest ideas for future content, or comment on something you’ve read on the Foundry Solutions … Read More
Marrying More Than Moore Technologies The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies, including 3D-IC, MEMS, and silicon photonics. This panel discusses the exciting opportunities and challenges ahead. Panelists John Ferguson, Director of Marketing, Calibre DRC Applications, … Read More
Achieving IC Reliability in High Growth Markets Several high-growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control, and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce new failure mechanisms. This panel discusses the demand for IC reliability, what design methodologies … Read More
Technical Article Just when you thought you were getting used to double patterning requirements and processes, multi-patterning is now a reality. While the additional MP requirements at 16/14 nm weren't readily visible to the designer, anyone moving to the 10 nm process node will probably need some additional multi-patterning education. The 10 nm node introduces at least two new multi-patterning … Read More
Expert’s Corner David Abercrombie, DFM Program Manager for Calibre, is an expert at detailing the multifaceted impacts of multi-patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of multi-patterning, his articles provide a well-lit roadmap that enables them to not only comprehend how multi-patterning will change the design process, … Read More
It’s all about communication. When I talk to people in the EDA community, we often bandy words around in the comfort that we all know what they mean — and that they mean the same thing to each of us. But do they? You know — what’s a model? A system? Tomato? Tomahto? I have been thinking a lot lately about hardware description languages — VHDL, VHDL-AMS, Verilog-AMS, SystemVerilog — and how we use words … Read More
Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More … Read More
There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More … Read More
Do FDSOI and FinFET provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI? Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits … Read More
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- TSMC OIP presentations now available!
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- March, 2014
- February, 2014
- January, 2014
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- July, 2013
- April, 2013
- March, 2013
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
- August, 2010
- June, 2010
- May, 2010
- April, 2010
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
- Calibre Everywhere -- the customer value of universal integration
- So, why not just write better rules?
- To be the man, you've gotta beat the man!
- Power in need, Power indeed
- May, 2009