IC Design Blog

Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass.  Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out.  Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC

Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More

Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, DRC, Sign-off, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC

I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight. Tezzaron Semiconductor … Read More

Deepchip, DRC, Calibre, Quartz, Tezzaron, LVS, Physical Verification

Clock designers are an enigma. Clock designers in general are die hard star wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in peak summer and have likeminded clock designers as best lunch buddies. Clock designers are notorious for making other lesser designers cry with their fancy PLL spice runs, non-negotiable … Read More

IC, Low Power

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More

Physical Verification, Yield, Design Quality, Design for Manufacturing, IC Verification, Leakage, DRC, IC Design

 When I was at PDF Solutions we launched a campaign that stated DFM is now the designer’s problem. It was not a resounding success as at 90nm, the majority of designers simply stated, “No it isn’t—it’s the fabs problem.”  While DFM was evolving and the major wrinkles were being ironed out, designers enjoyed a “grace period” when the dangers of not doing DFM checks were perhaps overstated, and the … Read More

Recently, I attended the latest OpenAccess (OA) conference put on by Si2. Attendance this year seemed to be up from last year. Whether the increased attendance was due to the increased adoption that we’ve seen in the industry or the fact that the conference was free this year is unclear. However, it is crystal clear that OA is no longer just a promise, and that adoption has moved from the true early … Read More

Calibre, Constraints, Adoption, OpenAccess, Interfaces, Interoperability

A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More

DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV

Then, as the old adage says, … “don’t do that.” Periodically, we get a complaint from someone who is becoming concerned about the time it takes to stream out GDSII from their P&R tool in order to run Calibre. We keep making Calibre faster and faster, so eventually the stream-out time starts to look big and hairy. In the typical final verification loop, you may have to do this whole stream, verify, fix, … Read More

Every so often it seems like we get a rash of “free trial” or “free software” offers in the EDA industry. Of course, in consumer goods where it makes a lot of sense, a free trial is one of the staple weapons in the marketing inventory. If you want someone to try a new or improved product that doesn’t require a big investment in time or effort to use, it’s a compelling way to generate interest. The question … Read More

Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for … Read More

ESD, PERC, Calibre

I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More

Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking

Now that almost all of the major custom design tools run on OpenAccess, we often get asked about how well Calibre supports OpenAccess (OA). The truth is that Calibre has supported reading polygonal data from OA since February 2007 and we have kept up with the new releases of OA as they come along. What has really driven adoption of OA in the last year or so has been the release of Virtuoso on OA, the … Read More

GDSII, PCELLs, Calibre

Taking liberties with Latin and Caesar’s “Veni, vidi, vici” line, I can say “Veni, vidi, steti.” I came, I saw, I stood. :=) While the main Mentor booth seemed to be quite busy the whole time, I was elsewhere working booth duty at the TSMC OIP pavilion. It was a nice, open space kind of like the vendor area at a TSMC tech forum. The TSMC booth was very busy on Monday, with a lot of people representing … Read More

DAC

My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP. It started … Read More

Design Quality, Design for Manufacturing, IP, Physical Verification, Yield