Expert’s Corner David Abercrombie, DFM Program Manager for Calibre, is an expert at detailing the multifaceted impacts of multi-patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of multi-patterning, his articles provide a well-lit roadmap that enables them to not only comprehend how multi-patterning will change the design process, … Read More
IC Design Blog
It’s all about communication. When I talk to people in the EDA community, we often bandy words around in the comfort that we all know what they mean — and that they mean the same thing to each of us. But do they? You know — what’s a model? A system? Tomato? Tomahto? I have been thinking a lot lately about hardware description languages — VHDL, VHDL-AMS, Verilog-AMS, SystemVerilog — and how we use words … Read More
Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More … Read More
There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More … Read More
Do FDSOI and FinFET provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI? Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits … Read More
I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield: “I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, … Read More
Here we go again, that wonderful time of year. No, not Christmas, DAC! Now is the time of year when all the EDA vendors are scurrying about finishing whatever it is they plan on doing at DAC. Since the business climate seems to be improving, it would be nice to see an increase in attendance. I like San Diego, I think it’s a great place to have DAC. Some think DAC is going the way of the Dodo, … Read More
Hello all, Just a friendly reminder, the Mentor Graphics User Group Meeting is just around the corner. It is scheduled for April 26th in Santa Clara, CA at the Santa Clara Marriott. If you are a Calibre user, this is your chance to get free access to information on Calibre’s and our roadmap as well as attend sessions on Mentor Graphics solutions in P&R, PCB, Custom IC design, and Test &… Read More
Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks. Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need … Read More
Almost 10 years ago, as the industry was starting to adopt model-based OPC and other resolution enhancing techniques on a large scale, the ITRS got out its looking glass and saw an “explosion” in the size of the files used to describe chip layouts. As a result, a group of industry companies collaborated to create a SEMI spec for the OASIS format for layout data. The format was officially … Read More
Density and the Analog Cell Analog design is a very sensitive business. Unlike the digital world, where circuits are on or off, and have built in hysteresis to prevent inadvertent toggling, analog circuitry is intentionally designed to respond to minor fluctuations in the signal. As a result, analog layout is riskier than digital. To prevent race conditions, or minor (yet potentially catastrophic) … Read More
For those of you who were wondering if I had fallen off the face of the planet, the answer is no. My mind was stuck in a limbo when I got hurt in an extraction (not the parasitic kind) mission. Confused? Read on… I finally got to watch the critically acclaimed sci-fi movie Inception last weekend and life has never been the same again. Without giving away too much detail for the benefit of those who … Read More
For customers who were unable to attend DAC this year, we are hosting Mentor @ DAC Extended. The registration is at: http://www.mentor.com/events/mentor-dac-extended/ What is Mentor @ DAC Extended? Mentor @ DAC Extended is an online presentation of 22 of our DAC 2010 suite sessions. Each 50 minute presentation includes: • presentation by technology area experts • live Q&A • an archive of the session … Read More
Just back from DAC in Anaheim. The last true Denali party was a smash. We’ll see if the tradition continues under new management. Nothing amazing to report about the show. Attendance seemed OK, though not stellar. Here’s an observation some may find interesting. I worked booth duty at both the TSMC OIP pavilion and the Global Foundries Global Solutions pavilion. At TSMC, the attendees needed to get … Read More
Mentor Graphics is excited to announce the launch of their new fast field solver for IC design, Calibre xACT 3D http://www.mentor.com/calibre-xact. This new tool is based Mentor Graphics’ acquisition of Pextra Corporation last year. This deterministic field solver has break-through performance, and excellent scalability, which enables the efficient use of multiple CPUs to achieve the fast turn-around-time. … Read More
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- TSMC OIP presentations now available!
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- March, 2014
- February, 2014
- January, 2014
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- July, 2013
- April, 2013
- March, 2013
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
- August, 2010
- June, 2010
- May, 2010
- April, 2010
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
- Calibre Everywhere -- the customer value of universal integration
- So, why not just write better rules?
- To be the man, you've gotta beat the man!
- Power in need, Power indeed
- May, 2009