When I was at PDF Solutions we launched a campaign that stated DFM is now the designer’s problem. It was not a resounding success as at 90nm, the majority of designers simply stated, “No it isn’t—it’s the fabs problem.”
While DFM was evolving and the major wrinkles were being ironed out, designers enjoyed a “grace period” when the dangers of not doing DFM checks were perhaps overstated, and the … Read More
Recently, I attended the latest OpenAccess (OA) conference put on by Si2. Attendance this year seemed to be up from last year. Whether the increased attendance was due to the increased adoption that we’ve seen in the industry or the fact that the conference was free this year is unclear. However, it is crystal clear that OA is no longer just a promise, and that adoption has moved from the true early … Read More
Calibre, Constraints, Adoption, OpenAccess, Interfaces, Interoperability
A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More
DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV
Then, as the old adage says, … “don’t do that.” Periodically, we get a complaint from someone who is becoming concerned about the time it takes to stream out GDSII from their P&R tool in order to run Calibre. We keep making Calibre faster and faster, so eventually the stream-out time starts to look big and hairy. In the typical final verification loop, you may have to do this whole stream, verify, fix, … Read More
Every so often it seems like we get a rash of “free trial” or “free software” offers in the EDA industry. Of course, in consumer goods where it makes a lot of sense, a free trial is one of the staple weapons in the marketing inventory. If you want someone to try a new or improved product that doesn’t require a big investment in time or effort to use, it’s a compelling way to generate interest. The question … Read More
Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools?
Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking.
If you’re interested, the paper is available on-line here:
New Flow for … Read More
I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More
Reliability, IC Verification, Yield, Design Quality, Design for Manufacturing, Scoring, Design Rules, IC Design, Physical Verification, Design Rule Checking
Now that almost all of the major custom design tools run on OpenAccess, we often get asked about how well Calibre supports OpenAccess (OA). The truth is that Calibre has supported reading polygonal data from OA since February 2007 and we have kept up with the new releases of OA as they come along. What has really driven adoption of OA in the last year or so has been the release of Virtuoso on OA, the … Read More
Taking liberties with Latin and Caesar’s “Veni, vidi, vici” line, I can say “Veni, vidi, steti.” I came, I saw, I stood. :=) While the main Mentor booth seemed to be quite busy the whole time, I was elsewhere working booth duty at the TSMC OIP pavilion. It was a nice, open space kind of like the vendor area at a TSMC tech forum. The TSMC booth was very busy on Monday, with a lot of people representing … Read More
My Monday started off well delivering the eqDRC presentation with Jim Culp. But I didn’t have long to enjoy it as I had to quickly head up to the mezzanine level to get ready for my lunch and learn event with ARM and Chartered. We have had a long relationship with both companies and we finally arranged to do a joint presentation on how we have collaborated to make more DFM compliant IP.
It started … Read More
Design Quality, Design for Manufacturing, IP, Physical Verification, Yield
I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More
IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking
Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More
Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules
Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More
IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking
So, I’ve “volunteered” to provide the occassional highlight of my DAC experience this year for Mentor Graphics. I was a little concerned about this, as I’ve been affraid this was going to be a rather lack-lustre event. Unfortunately, I have to say that so far my expectations have been dead on. But, due to a little serendipity, I did stumble upon something that at least sparked some thought and interest.
On … Read More
EDA Roadmap, SiP, DAC, TSV
In my last post I discussed the reasons and challenges associated with “waivers” for DRC. As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex. To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage. Not only is the DRC debug … Read More