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IC Design Blog

13 Dec, 2013

Shelly Stalnaker No one wants to edit a foundry rule deck—it’s like tugging on Superman’s cape. But there are many ways to customize the input to a Calibre job without modifying the foundry rule deck. To learn more, watch one of our short, to-the-point How-To videos on our IC Nanometer Design channel on YouTube. Oh, and if you can’t find what you’re looking for? Suggest a new topic! … Read More

runsets, rule decks, configurations, DRC, Calibre, rule checks, ERC, Foundry

13 Dec, 2013

Model-Based Hints: GPS for LFD Success

Posted by Shelly Stalnaker

Shelly Stalnaker Personal GPS systems were a blessing for directionally-challenged people. Model-based hinting (MBH) for LFD hotspot corrections evoke a similar feeling of relief in engineers who are tired of late-night stints trying to figure out how to correct a litho hotspot without creating even more problems. MBH can evaluate your fix options and identify which ones are viable, helping you make better decisions … Read More

hotspots, LFD, Calibre, model-based hints, litho, MBH

21 Oct, 2013

No Fear of FinFET

Posted by Shelly Stalnaker

Shelly Stalnaker No Fear of FinFET FinFETs, or so-called 3D transistors, are a key competitive element in all the leading-edge IC foundry offerings, because FinFETs can achieve much lower power operation than planar transistors. This panel discusses how FinFETs will change the design, verification, and test flow. Panelists Joe Sawicki, VP and General Manager of the Design to Silicon Division, Mentor Graphics KK Lin, … Read More

7 Oct, 2013

Simon Favre At the recent TSMC OIP, I had an interesting discussion with a TSMC employee (who shall remain nameless), regarding 450mm wafers. The gist of the discussion was that EUV has become a gating item for the move to 450mm wafers. Why are these two related? They are connected at the purse strings. It will cost billions (with a B) to build a 450mm wafer fab. It will cost billions to go to EUV. Why pay this … Read More

TSMC EUV 450mm

1 Oct, 2013

Shelly Stalnaker I’ve just taken over editorial responsibilities for the Foundry Solutions content, and I look forward to bringing you the information and guidance you need to deliver innovative and profitable designs to the market. Our job and our goal is to help you get to tapeout on time, with confidence! Please feel free to suggest ideas for future content, or comment on something you’ve read on the Foundry Solutions … Read More

29 Sep, 2013

Marrying More Than Moore Technologies

Posted by Shelly Stalnaker

Shelly Stalnaker Marrying More Than Moore Technologies The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies, including 3D-IC, MEMS, and silicon photonics. This panel discusses the exciting opportunities and challenges ahead. Panelists John Ferguson, Director of Marketing, Calibre DRC Applications, … Read More

27 Sep, 2013

Shelly Stalnaker Achieving IC Reliability in High Growth Markets Several high-growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control, and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce new failure mechanisms. This panel discusses the demand for IC reliability, what design methodologies … Read More

25 Sep, 2013

Shelly Stalnaker Technical Article Just when you thought you were getting used to double patterning requirements and processes, multi-patterning is now a reality. While the additional MP requirements at 16/14 nm weren't readily visible to the designer, anyone moving to the 10 nm process node will probably need some additional multi-patterning education. The 10 nm node introduces at least two new multi-patterning … Read More

23 Sep, 2013

Multi-Patterning Unmasked!!

Posted by Shelly Stalnaker

Shelly Stalnaker Expert’s Corner David Abercrombie, DFM Program Manager for Calibre, is an expert at detailing the multifaceted impacts of multi-patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of multi-patterning, his articles provide a well-lit roadmap that enables them to not only comprehend how multi-patterning will change the design process, … Read More

23 Jul, 2013

What’s in a Name: Signal

Posted by Martin Vlach

Martin Vlach It’s all about communication. When I talk to people in the EDA community, we often bandy words around in the comfort that we all know what they mean — and that they mean the same thing to each of us. But do they? You know — what’s a model? A system? Tomato? Tomahto? I have been thinking a lot lately about hardware description languages — VHDL, VHDL-AMS, Verilog-AMS, SystemVerilog — and how we use words … Read More

wreal, analog signal, connect module, analog abstraction, event-driven model, real number model, digital abstraction, digital signal

5 Apr, 2013

The Secrets of 14nm Lithography

Posted by Gene Forte

Gene Forte Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More … Read More

SRAF, RET, 20nm, 22 nm, 14nm, manufacturability, OPC, Foundry, Lithography

19 Mar, 2013

A New World for Fill at N20

Posted by admin

admin There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More … Read More

fill, 20nm, litho, N20

7 Dec, 2012

Battle of Fins and BOXes

Posted by Arvind Narayanan

Arvind Narayanan Do FDSOI and FinFET provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI?  Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits … Read More

FD-SOI, fin grid, dual gate, MugFET, Tri-gate, FinFET, full depleted SOI

5 Mar, 2012

TSMC 28nm yield (SemiWiki)

Posted by Simon Favre

Simon Favre I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield: “I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, … Read More

CAA, TSMC, 28nm

11 May, 2011

DAC 2011 is upon us!

Posted by Simon Favre

Simon Favre Here we go again, that wonderful time of year. No, not Christmas, DAC! Now is the time of year when all the EDA vendors are scurrying about finishing whatever it is they plan on doing at DAC. Since the business climate seems to be improving, it would be nice to see an increase in attendance. I like San Diego, I think it’s a great place to have DAC. Some think DAC is going the way of the Dodo, … Read More

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