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IC Design Blog

19 Mar, 2013

A New World for Fill at N20

Posted by admin

admin There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More … Read More

fill, 20nm, litho, N20

7 Dec, 2012

Battle of Fins and BOXes

Posted by Arvind Narayanan

Arvind Narayanan Do FDSOI and FinFET provide better performance and better power than bulk? Will FDSOI at 20nm bridge the 16nm finFET gap? Does finFET offer better cost benefits than FDSOI?  Does shamwow actually hold 20 times its weight in liquid? While the last claim is questionable, the jury is not out yet on the FDSOI vs. FinFET war. Proponents of both these technologies claim significant power and performance benefits … Read More

FD-SOI, fin grid, dual gate, MugFET, Tri-gate, FinFET, full depleted SOI

5 Mar, 2012

TSMC 28nm yield (SemiWiki)

Posted by Simon Favre

Simon Favre I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield: “I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, … Read More

CAA, TSMC, 28nm

11 May, 2011

DAC 2011 is upon us!

Posted by Simon Favre

Simon Favre Here we go again, that wonderful time of year. No, not Christmas, DAC! Now is the time of year when all the EDA vendors are scurrying about finishing whatever it is they plan on doing at DAC. Since the business climate seems to be improving, it would be nice to see an increase in attendance. I like San Diego, I think it’s a great place to have DAC. Some think DAC is going the way of the Dodo, … Read More

11 Apr, 2011

Mentor Graphics User to User (U2U)

Posted by John Ferguson

John Ferguson

Hello all, Just a friendly reminder, the Mentor Graphics User Group Meeting is just around the corner. It is scheduled for April 26th in Santa Clara, CA at the Santa Clara Marriott. If you are a Calibre user, this is your chance to get free access to information on Calibre’s and our roadmap as well as attend sessions on Mentor Graphics solutions in P&R, PCB, Custom IC design, and Test &

Read More

10 Feb, 2011

Matthew Hogan Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks. Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need … Read More

Low Power, PERC, ERC, thin oxide, Verification

22 Jan, 2011

Dawn at the OASIS

Posted by Joe Davis

Joe Davis Almost 10 years ago, as the industry was starting to adopt model-based OPC and other resolution enhancing techniques on a large scale, the ITRS got out its looking glass and saw an “explosion” in the size of the files used to describe chip layouts. As a result, a group of industry companies collaborated to create a SEMI spec for the OASIS format for layout data. The format was officially … Read More

diffusion of innovation, GDSII, Adoption, RET, tape-out, OASIS, OPC

29 Nov, 2010

Layout Density and the Analog Cell

Posted by John Ferguson

John Ferguson Density and the Analog Cell Analog design is a very sensitive business. Unlike the digital world, where circuits are on or off, and have built in hysteresis to prevent inadvertent toggling, analog circuitry is intentionally designed to respond to minor fluctuations in the signal. As a result, analog layout is riskier than digital. To prevent race conditions, or minor (yet potentially catastrophic) … Read More

density, DRC, analog, layout

20 Aug, 2010

Effects of Inception

Posted by Arvind Narayanan

Arvind Narayanan For those of you who were wondering if I had fallen off the face of the planet, the answer is no. My mind was stuck in a limbo when I got hurt in an extraction (not the parasitic kind) mission. Confused? Read on… I finally got to watch the critically acclaimed sci-fi movie Inception last weekend and life has never been the same again. Without giving away too much detail for the benefit of those who … Read More

Donut Domains, Multi-Voltage Flow, always-on, UPF

21 Jun, 2010

Simon Favre Just back from DAC in Anaheim. The last true Denali party was a smash. We’ll see if the tradition continues under new management. Nothing amazing to report about the show. Attendance seemed OK, though not stellar. Here’s an observation some may find interesting. I worked booth duty at both the TSMC OIP pavilion and the Global Foundries Global Solutions pavilion. At TSMC, the attendees needed to get … Read More

GF, DAC

2 Jun, 2010

Enabling Superior Support

Posted by John Ferguson

John Ferguson In my last few posts, I began discussing on what it takes to enable software quality and support.  This particular post will focus on the latter, support. Of course the goal of any descent software provider is to deliver software that is bug free, intuitive to use, and performs a valuable service.  While we strive for perfection, in reality these goals can never be fully achieved.  In the EDA world, … Read More

Mentor Graphics, Physical Verification, Calibre, Support

11 May, 2010

Simon Favre This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More

Redundancy, CAA, SoC, SRAM

15 Apr, 2010

Economy must be improving

Posted by Simon Favre

Simon Favre If attendance at the TSMC Technology Symposium in San Jose (link redirects) is any indicator, the economy must be improving. Official attendance was said to be 1500, but it felt like it was more. Of course, there were a lot of TSMC staff milling about, and they did have 2 of the booths in the vendor area for their own offerings, but there were still a lot of people there. The thing EDA vendors like … Read More

Economy

18 Mar, 2010

Simon Favre The recent earthquake in Taiwan did have an impact on TSMC’s production, but probably not as great as some in the press have indicated:  TSMC loses 40K wafers in quake. This blog gives a more careful reading of the announcement. What it comes down to is “1.5 days loss of wafer movement for the company in total.” Regardless of whether or not they had to scrap any wafers, 1.5 days of downtime is 1.5 … Read More

earthquake

15 Mar, 2010

Assuring Software Quality

Posted by John Ferguson

John Ferguson In my last blog I discussed the importance of support and the value it provides in the physical verification space.  As indicated, one of the key components in providing support is having an infrastructure helps to assure quality software releases in the first place.  In this blog, I will provide more insight into the procedures in place within the Calibre organization that help to ensure the high standards … Read More

DRC, Mentor, Calibre, Physical Verificaiton, PV

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