In my last blog I discussed the importance of support and the value it provides in the physical verification space. As indicated, one of the key components in providing support is having an infrastructure helps to assure quality software releases in the first place. In this blog, I will provide more insight into the procedures in place within the Calibre organization that help to ensure the high standards … Read More
IC Design Blog
Step 0 Commitment – Are you really sure you want to MV? Are you positive that Multi-Vt & Clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must. Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done … Read More
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
When asked about the value that the Calibre platform brings to the design community, most folks will respond with performance, foundry support, and ease of debugging. While these are all valuable aspects and traits of Calibre, there is one more benefit that is often taken for granted: support. The word “support” is something bandied around loosely in EDA. Saying you have good support is akin to saying … Read More
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More
I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight. Tezzaron Semiconductor … Read More
Clock designers are an enigma. Clock designers in general are die hard star wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in peak summer and have likeminded clock designers as best lunch buddies. Clock designers are notorious for making other lesser designers cry with their fancy PLL spice runs, non-negotiable … Read More
In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More
When I was at PDF Solutions we launched a campaign that stated DFM is now the designer’s problem. It was not a resounding success as at 90nm, the majority of designers simply stated, “No it isn’t—it’s the fabs problem.” While DFM was evolving and the major wrinkles were being ironed out, designers enjoyed a “grace period” when the dangers of not doing DFM checks were perhaps overstated, and the … Read More
Recently, I attended the latest OpenAccess (OA) conference put on by Si2. Attendance this year seemed to be up from last year. Whether the increased attendance was due to the increased adoption that we’ve seen in the industry or the fact that the conference was free this year is unclear. However, it is crystal clear that OA is no longer just a promise, and that adoption has moved from the true early … Read More
A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More
Then, as the old adage says, … “don’t do that.” Periodically, we get a complaint from someone who is becoming concerned about the time it takes to stream out GDSII from their P&R tool in order to run Calibre. We keep making Calibre faster and faster, so eventually the stream-out time starts to look big and hairy. In the typical final verification loop, you may have to do this whole stream, verify, fix, … Read More
Every so often it seems like we get a rash of “free trial” or “free software” offers in the EDA industry. Of course, in consumer goods where it makes a lot of sense, a free trial is one of the staple weapons in the marketing inventory. If you want someone to try a new or improved product that doesn’t require a big investment in time or effort to use, it’s a compelling way to generate interest. The question … Read More
Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for … Read More
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- TSMC OIP presentations now available!
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- March, 2014
- February, 2014
- January, 2014
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- July, 2013
- April, 2013
- March, 2013
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
- August, 2010
- June, 2010
- May, 2010
- April, 2010
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
- Calibre Everywhere -- the customer value of universal integration
- So, why not just write better rules?
- To be the man, you've gotta beat the man!
- Power in need, Power indeed
- May, 2009