Diamonds may not be a designer’s best friend when debugging triple patterning errors. Triple patterning violations can be quite complex, and debugging can be tricky, but the challenges are manageable with software that helps the designer understand the design issues. Learn how to recognize and avoid triple patterning traps in part 2 of The Trouble with Triples on SemiEngineering by multi-patterning … Read More
IC Design Blog
Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference. Design Reliability with Calibre YE-SmartFill and Calibre PERC (Broadcom & Mentor Graphics) New methodologies were developed for 28nm designs using Calibre SmartFill and Calibre PERC. Calibre SmartFill was deployed to meet the new strict DFM requirements … Read More
All the major foundries have announced FinFET technologies. FinFETs hold the promise of lower power usage and better area utilization, as well as traditional scaling improvements. Aaaaand…the thought of implementing them may be scaring the willies out of a lot of designers. How do I design these things? How do I know what the design needs? How do I verify them? Well, first, take a deep breath. … Read More
What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More
DRC- and DFM-clean designs can still have hundreds to thousands of violations that must be debugged and corrected. How? Why? Mismatches between a router’s simplified tech file and the complete (and complex) signoff design rule decks at advanced nodes are generating significant numbers of DRC/DFM errors that can wreak havoc on your tapeout schedules. In particular, we’re seeing greater visibility … Read More
It happens all the time, to all of us. You need a quick answer for a very specific question about using your EDA tools. You don’t want to wade through technical documentation, you don’t have time for an email response, and you really don’t want to try searching EDA forums for an answer. We feel your pain, and we decided to do something about it. Need to know how to extract a net from … Read More
Press releases can make it seem like EDA tool qualification for a particular IC process node is the “end game.” But in truth, qualification is just the first publicly visible step of ongoing collaborations between an EDA vendor and the foundry. Michael White takes you behind the curtain for a peek at what goes on during qualification from start to finish, as part of his ongoing Silicon Edge series … Read More
Just like blueprints give an architect a visual representation of a building, design patterns provide engineers with a visual depiction of complex layout geometries. Design patterns have become a useful tool throughout design, verification, and test processes. This Design-to-Silicon white paper explains how Calibre Pattern Matching software can help you implement automated pattern capture and pattern … Read More
While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. In this white paper from David Abercrombie, learn what multi-patterning is, why you need it, and how Calibre Multi-Patterning software … Read More
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Triple patterning is not just double patterning with an extra color! Our resident expert, David Abercrombie, introduces the basics of triple patterning and explains the new challenges it brings to the layout and verification flow in his ongoing series for for SemiconductorEngineering’s Manufacturing and Design segment. If you’re even thinking about advanced node designs, this is a must-read. Bonus references … Read More
Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More
The need for high reliability covers a wide array of market segments, all with differing acceptance requirements. In this video, Matt Hogan explores the challenges of comprehensive reliability verification, and demonstrates how Calibre PERC can help you satisfy the most demanding requirements with confidence. … Read More
No one wants to edit a foundry rule deck—it’s like tugging on Superman’s cape. But there are many ways to customize the input to a Calibre job without modifying the foundry rule deck. To learn more, watch one of our short, to-the-point How-To videos on our IC Nanometer Design channel on YouTube. Oh, and if you can’t find what you’re looking for? Suggest a new topic! … Read More
Personal GPS systems were a blessing for directionally-challenged people. Model-based hinting (MBH) for LFD hotspot corrections evoke a similar feeling of relief in engineers who are tired of late-night stints trying to figure out how to correct a litho hotspot without creating even more problems. MBH can evaluate your fix options and identify which ones are viable, helping you make better decisions … Read More
No Fear of FinFET FinFETs, or so-called 3D transistors, are a key competitive element in all the leading-edge IC foundry offerings, because FinFETs can achieve much lower power operation than planar transistors. This panel discusses how FinFETs will change the design, verification, and test flow. Panelists Joe Sawicki, VP and General Manager of the Design to Silicon Division, Mentor Graphics KK Lin, … Read More
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- TSMC OIP presentations now available!
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- March, 2014
- February, 2014
- January, 2014
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- July, 2013
- April, 2013
- March, 2013
- December, 2012
- March, 2012
- May, 2011
- April, 2011
- February, 2011
- January, 2011
- November, 2010
- August, 2010
- June, 2010
- May, 2010
- April, 2010
- March, 2010
- February, 2010
- January, 2010
- December, 2009
- November, 2009
- October, 2009
- September, 2009
- August, 2009
- July, 2009
- June, 2009
- "Waive" of the Future?
- How do you debug LVS?
- DFM for Non-PhD's: Part 2 - Reliability
- Mixed-Signal SoC Verification
- Process Variation: The Use of In-Die Variation
- DFM for Non-PhDs
- Calibre Everywhere -- the customer value of universal integration
- So, why not just write better rules?
- To be the man, you've gotta beat the man!
- Power in need, Power indeed
- May, 2009