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IC Design Blog

Posts tagged with '20nm'

19 Mar, 2014

Déjà Vu All Over Again

Posted by Shelly Stalnaker

Shelly Stalnaker Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm … Read More

Foundry, IC Design, 14nm, 16nm, 10nm, advanced node, leading-edge, Semiconductor, Christen Decoin, 20nm, technology node, 28nm

18 Mar, 2014

Old Faithful

Posted by Shelly Stalnaker

Shelly Stalnaker While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More

IC Design, Foundry Solutions, IC Verification, 16nm, 20nm, 10nm, circuit, PERC, Reliability, electrical, 45nm, Verification, Calibre

14 Mar, 2014

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

3 Mar, 2014

Lights! Camera! Multi-Patterning!

Posted by Shelly Stalnaker

Shelly Stalnaker David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More

double patterning, EUV, 20nm, Multi-Patterning, triple patterning, IC Design, ic manufacturing

15 Jan, 2014

2014 is Underway! What's on Your Calendar?

Posted by Shelly Stalnaker

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

13 Dec, 2013

Mastering the Magic of Multi-Patterning

Posted by Shelly Stalnaker

Shelly Stalnaker While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. In this white paper from David Abercrombie, learn what multi-patterning is, why you need it, and how Calibre Multi-Patterning software … Read More

odd cycle, multipatterning, 16nm, Lithography, 20nm, mandrel, Mentor Graphics, Multi-Patterning, 14nm, colorless design, layout decomposition, D2S, LELE, anchor path, litho, Calibre Multi-Patterning, litho-etch-litho-etch, FinFET, double patterning, Foundry, warning rings, Parasitic Extraction, spacer-assisted, triple patterning, spacer is dielectric, spacer is mask, SID SADP, SIM SADP, pin coloring, pitch-split

13 Dec, 2013

The Trouble With Triples—Part 1

Posted by Shelly Stalnaker

Shelly Stalnaker Triple patterning is not just double patterning with an extra color! Our resident expert, David Abercrombie, introduces the basics of triple patterning and explains the new challenges it brings to the layout and verification flow in his ongoing series for for SemiconductorEngineering’s Manufacturing and Design segment. If you’re even thinking about advanced node designs, this is a must-read. Bonus references … Read More

Foundry, DRC, multipatterning, 14nm, 16nm, 10nm, triple patterning, double patterning, 20nm, decomposition

13 Dec, 2013

Shelly Stalnaker Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More

DRC, digital IC, Foundry, tech files, tapeout, 14nm, rule decks, signoff, 16nm, SoC, 10nm, SVRF, IP, Design Rule Checking, P&R, router, 20nm, Routing, Debugging

5 Apr, 2013

The Secrets of 14nm Lithography

Posted by Gene Forte

Gene Forte Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More … Read More

SRAF, RET, 20nm, 22 nm, 14nm, manufacturability, OPC, Foundry, Lithography

19 Mar, 2013

A New World for Fill at N20

Posted by admin

admin There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More … Read More

fill, 20nm, litho, N20

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