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IC Design Blog

Posts tagged with '45nm'

18 Mar, 2014

Old Faithful

Posted by Shelly Stalnaker

Shelly Stalnaker While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More

IC Design, IC Verification, 16nm, 20nm, 10nm, circuit, PERC, Reliability, electrical, 45nm, Verification, Calibre

14 Mar, 2014

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

8 Jul, 2009

What do you mean by mandatory?

Posted by Simon Favre

Simon Favre TSMC and Mentor Graphics recently held a joint Marketing seminar (06/25/09) for mutual customers to go over the new DFM requirements at 45/40 nm. (In my first post, I mused about the implications of making some DFM analysis steps mandatory.) When the presentations at the seminar ended, and the Q&A began, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC … Read More


2 Jun, 2009

So, why not just write better rules?

Posted by Simon Favre

Simon Favre In my previous post about TSMC making some DFM analysis steps mandatory at 45nm, I ended with a question about why the foundries can't just write better design rules (and rule decks) to make sure all designs yield well. This is a topic that has been discussed elsewhere, but here's my take on it. If we take a step back for a moment, there is something generic about DFM analysis that needs to be considered. … Read More

DRC, 45nm

22 May, 2009

TSMC's DFM Announcement

Posted by Simon Favre

Simon Favre If you are a TSMC customer, no doubt you have heard that TSMC has announced that for 45nm (and presumably beyond), LPC and VCMP are mandatory for block/chip. What does this mean? It means that TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for … Read More



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