I posted the following reply to Daniel Nenni’s article on TSMC 28nm yield:
“I agree that design teams need to take more ownership of the yield issue. Unfortunately, yield is such a sensitive topic that people only talk about it when it’s bad! The defect density vs. die size and yield curves above represent the simplest area-based yield model, based on an average across many designs, … Read More
IC Design Blog
Posts tagged with 'CAA'
5
Mar, 2012
11
May, 2010
This week, I’m off to present a paper on Critical Area Analysis and Memory Redundancy. It’s at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. IBM is in Fishkill. IBM invented CAA in what, the 1960’s? Venturing into IBM country to speak on Critical Area Analysis is kind of like being the court jester. I just hope they don’t say, “Off with his head.” … Read More
Redundancy, CAA, SoC, SRAM
Recent Posts
- Battle of Fins and BOXes
- TSMC 28nm yield (SemiWiki)
- DAC 2011 is upon us!
- Mentor Graphics User to User (U2U)
- Gate Oxide Breakdown Failures Highlight Industry Need for New Electrical Rule Checking Tools
- Dawn at the OASIS
- Layout Density and the Analog Cell
- Effects of Inception
- On-line session covering the DAC presentation for Calibre xACT 3D
- You can't give stuff away fast enough