Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools?
Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking.
If you’re interested, the paper is available on-line here:
New Flow for … Read More
IC Design Blog
Posts tagged with 'Calibre'
Now that almost all of the major custom design tools run on OpenAccess, we often get asked about how well Calibre supports OpenAccess (OA). The truth is that Calibre has supported reading polygonal data from OA since February 2007 and we have kept up with the new releases of OA as they come along. What has really driven adoption of OA in the last year or so has been the release of Virtuoso on OA, the … Read More
In my last post I discussed the reasons and challenges associated with “waivers” for DRC. As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex. To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage. Not only is the DRC debug … Read More
Thanks everyone for voting on my posting:
Fun and edgy parasitic extraction blog?
Since I didn’t exactly get consensus on what topic I should work on next, I thought I’d pick two topics that a few of you wanted. Here it goes:
Topic 15: Why my previous car was named Bob?
Answer:
My old white Toyota Camry was called Bob, because it was sooooooo boring that I named it the most boring name I could … Read More
DAC is less than two months away… and the phone is starting to ring again…saying “We are doing demos and realize that we are showing Calibre everywhere. Do you want to participate in our demos?” Of course we do
Our approach has always been to make Calibre available in every design tool and on every database. This approach is good for everyone. Designs have to be certified “clean” (more on that in … Read More
Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future…
Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout … Read More
Verilog, SPICE, Calibre_LVS, Hierarchical LVS, Calibre, Netlist, nmLVS, Hierarchical_LVS, LVS
Hi everyone, and welcome to my first blog entry. When I found out that I was going to be writing a blog on parasitic extraction, my first thoughts were:
Blog = fun, edgy, exciting
Parasitic extraction = geeky, techie, boring
Therefore,
Blog ≠ Parasitic Extraction
How was I going to make this work? How am I going to make model order reduction and stochastic integral equation solvers and nanometer … Read More
Recent Posts
- Battle of Fins and BOXes
- TSMC 28nm yield (SemiWiki)
- DAC 2011 is upon us!
- Mentor Graphics User to User (U2U)
- Gate Oxide Breakdown Failures Highlight Industry Need for New Electrical Rule Checking Tools
- Dawn at the OASIS
- Layout Density and the Analog Cell
- Effects of Inception
- On-line session covering the DAC presentation for Calibre xACT 3D
- You can't give stuff away fast enough