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IC Design Blog

Posts tagged with 'Calibre'

26 Oct, 2009

14th OpenAccess Conference

Posted by Joe Davis

Joe Davis Recently, I attended the latest OpenAccess (OA) conference put on by Si2. Attendance this year seemed to be up from last year. Whether the increased attendance was due to the increased adoption that we’ve seen in the industry or the fact that the conference was free this year is unclear. However, it is crystal clear that OA is no longer just a promise, and that adoption has moved from the true early … Read More

Calibre, Constraints, Adoption, OpenAccess, Interfaces, Interoperability

30 Sep, 2009

The Biggest Loser?

Posted by John Ferguson

John Ferguson A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More

DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV

30 Aug, 2009

ESD Design Rule Checking

Posted by Matthew Hogan

Matthew Hogan Verification of ESD structures and other protection circuits is often a time consuming and tedious task. How do you do it? Complex DRC rules? An assortment of specialized rule decks? Home-brew tools? Recently a colleague and I published a paper which used one of the Mentor tools (Calibre® PERC) to help with this ESD checking. If you’re interested, the paper is available on-line here: New Flow for … Read More

ESD, PERC, Calibre

14 Aug, 2009

Joe Davis Now that almost all of the major custom design tools run on OpenAccess, we often get asked about how well Calibre supports OpenAccess (OA). The truth is that Calibre has supported reading polygonal data from OA since February 2007 and we have kept up with the new releases of OA as they come along. What has really driven adoption of OA in the last year or so has been the release of Virtuoso on OA, the … Read More

GDSII, PCELLs, Calibre

21 Jul, 2009

Waive Bye-Bye

Posted by John Ferguson

John Ferguson In my last post I discussed the reasons and challenges associated with “waivers” for DRC.  As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex.  To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage.  Not only is the DRC debug … Read More

Physical Verification, DRC, Calibre, DAC, Waivers

8 Jun, 2009

Karen Chow Thanks everyone for voting on my posting: Fun and edgy parasitic extraction blog? Since I didn’t exactly get consensus on what topic I should work on next, I thought I’d pick two topics that a few of you wanted. Here it goes: Topic 15: Why my previous car was named Bob? Answer: My old white Toyota Camry was called Bob, because it was sooooooo boring that I named it the most boring name I could … Read More

Calibre xRC, In-Die Variation, Calibre, Process Variation

3 Jun, 2009

Joe Davis DAC is less than two months away… and the phone is starting to ring again…saying “We are doing demos and realize that we are showing Calibre everywhere. Do you want to participate in our demos?” Of course we do Our approach has always been to make Calibre available in every design tool and on every database. This approach is good for everyone.  Designs have to be certified “clean” (more on that in … Read More

DRC, IC, Calibre

28 May, 2009

Source Netlist Creation for LVS

Posted by Matthew Hogan

Matthew Hogan Hopefully you’ll find the current and future content posted here interesting enough that you’ll come back and share own opinions, thoughts and ideas. Please let me know if there are specific topics you’re interested in. Maybe we can look at these in the future… Today, I’d like to explore the task of creating a trusted source netlist that is used as the template for comparison to prove that your layout … Read More

Verilog, SPICE, Calibre_LVS, Hierarchical LVS, Calibre, Netlist, nmLVS, Hierarchical_LVS, LVS

20 May, 2009

Karen Chow Hi everyone, and welcome to my first blog entry. When I found out that I was going to be writing a blog on parasitic extraction, my first thoughts were: Blog = fun, edgy, exciting Parasitic extraction = geeky, techie, boring Therefore, Blog ≠ Parasitic Extraction How was I going to make this work? How am I going to make model order reduction and stochastic integral equation solvers and nanometer … Read More

Parasitic Extraction, Calibre

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