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IC Design Blog

Posts tagged with 'connect module'

23 Jul, 2013

What’s in a Name: Signal

Posted by Martin Vlach

Martin Vlach It’s all about communication. When I talk to people in the EDA community, we often bandy words around in the comfort that we all know what they mean — and that they mean the same thing to each of us. But do they? You know — what’s a model? A system? Tomato? Tomahto? I have been thinking a lot lately about hardware description languages — VHDL, VHDL-AMS, Verilog-AMS, SystemVerilog — and how we use words … Read More

wreal, analog signal, connect module, analog abstraction, event-driven model, real number model, digital abstraction, digital signal


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