Just back from DAC in Anaheim. The last true Denali party was a smash. We’ll see if the tradition continues under new management. Nothing amazing to report about the show. Attendance seemed OK, though not stellar.
Here’s an observation some may find interesting. I worked booth duty at both the TSMC OIP pavilion and the Global Foundries Global Solutions pavilion. At TSMC, the attendees needed to get … Read More
Taking liberties with Latin and Caesar’s “Veni, vidi, vici” line, I can say “Veni, vidi, steti.” I came, I saw, I stood. :=) While the main Mentor booth seemed to be quite busy the whole time, I was elsewhere working booth duty at the TSMC OIP pavilion. It was a nice, open space kind of like the vendor area at a TSMC tech forum. The TSMC booth was very busy on Monday, with a lot of people representing … Read More
I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More
Tags: IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking
Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More
Tags: Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules
Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More
Tags: IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Power, Design Rule Checking
So, I’ve “volunteered” to provide the occassional highlight of my DAC experience this year for Mentor Graphics. I was a little concerned about this, as I’ve been affraid this was going to be a rather lack-lustre event. Unfortunately, I have to say that so far my expectations have been dead on. But, due to a little serendipity, I did stumble upon something that at least sparked some thought and interest.
On … Read More
Tags: EDA Roadmap, SiP, DAC, TSV
In my last post I discussed the reasons and challenges associated with “waivers” for DRC. As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex. To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage. Not only is the DRC debug … Read More
Tags: Physical Verification, DRC, Calibre, DAC, Waivers
