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IC Design Blog

Posts tagged with 'DRC'

15 Jan, 2010

Michael White Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass.  Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out.  Your design team is now constantly waiving over and over and … Read More

Foundry, Foundries, IC Design, DRC, SVRF, Tax, Waiver, Calibre, Physical Verification, Fab-lite, Productivity, Fabless, Sign-off, eqDRC, SoC, Equation-Based DRC

17 Dec, 2009

Does SVRF Direct Read Make Sense?

Posted by Michael White

Michael White Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers. Why Do Competing PV Products Want to Use Calibre SVRF? Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More

Foundries, Fabless, Foundry, TVF, Translators, Direct Read, PV, Sign-off, DRC, SVRF, Calibre, Syntax, IC Design, Equation-Based DRC, IDM, Fab-lite, Native Read, Physical Verification, eqDRC

15 Dec, 2009

John Ferguson I don’t normally take the time to respond to any of the various competitive claims out there. But recently in ESNUG 483, item #2, there was a posting entitled “We recently dumped Mentor Calibre for Magma Quartz DRC/LVS” (http://www.deepchip.com/items/0483-02.html) that I feel needs to be addressed because it is misleading. So let me lay out the facts to set the record straight. Tezzaron Semiconductor … Read More

Deepchip, DRC, Calibre, Quartz, Tezzaron, LVS, Physical Verification

20 Nov, 2009

IBM Addresses Leakage

Posted by David Abercrombie

David Abercrombie

In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield

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Physical Verification, Yield, DRC, Leakage, IC Design, Design Quality, IC Verification, Design for Manufacturing

30 Sep, 2009

The Biggest Loser?

Posted by John Ferguson

John Ferguson A new season of NBC’s “The Biggest Loser” recently started. Have you seen this show? My wife, Cherie, loves it; she finds it inspirational to watch these folks put them through such a tough ordeal in order to improve their health. I enjoy it as well, though my motives are completely different. There are some pretty large individuals on that show. Somehow watching them makes me feel less self-conscious … Read More

DRC, Performance, Calibre, Runtime, Scaling, Physical Verification, PV

4 Aug, 2009

David's DAC09 - White Paper Session

Posted by David Abercrombie

David Abercrombie I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More

IC Verification, IC Design, DAC, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

31 Jul, 2009

David's DAC09 - Another Special Guest

Posted by David Abercrombie

David Abercrombie Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More

Reliability, IC Verification, Yield, Physical Verification, Design for Manufacturing, DAC, DRC, IC Design, Improvability, Design Rule Checking, Design Rules

28 Jul, 2009

David's DAC09 - Off to a great start!

Posted by David Abercrombie

David Abercrombie Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More

IC Verification, IC Design, Yield, Design Quality, Design for Manufacturing, DAC, Design Rules, Leakage, DRC, Physical Verification, Design Rule Checking

21 Jul, 2009

Waive Bye-Bye

Posted by John Ferguson

John Ferguson In my last post I discussed the reasons and challenges associated with “waivers” for DRC.  As discused, this is becoming a bigger and bigger challenge as designs become more intricate and design rules become more complex.  To the poor design team that has the challenge of integrating IP from multiple sources into a single working design, this can become a nightmare to manage.  Not only is the DRC debug … Read More

Physical Verification, DRC, Calibre, DAC, Waivers

2 Jul, 2009

To Waive Or Not To Waive?

Posted by David Abercrombie

David Abercrombie That is the question! If you read my colleague John’s most recent posting “Waive of the future?”, you will understand the question. I was equally shocked as John to find that almost no one tapes out DRC clean anymore. I would add one other reason to John’s list as to why this has happened. I think the traditional DRC rules are broken. Please read my first post “Are Design Rules Broken?” for my stance … Read More

IC Verification, IC Design, Design Quality, Design for Manufacturing, Design Rules, DRC, Physical Verification, Design Rule Checking

30 Jun, 2009

"Waive" of the Future?

Posted by John Ferguson

John Ferguson Many, many years ago, when I started in this business, I encountered something that I thought was surprising.  In my very first DRC benchmark, I was struggling with a particular rule.  The customer had given me a 0.25 micron layout, which they had successfully taped out.  My job was to write a rule file in the new tool to measure performance improvement.  My code matched the design rule manual and passed … Read More

IC Design, DRC

3 Jun, 2009

Joe Davis DAC is less than two months away… and the phone is starting to ring again…saying “We are doing demos and realize that we are showing Calibre everywhere. Do you want to participate in our demos?” Of course we do Our approach has always been to make Calibre available in every design tool and on every database. This approach is good for everyone.  Designs have to be certified “clean” (more on that in … Read More

DRC, IC, Calibre

2 Jun, 2009

So, why not just write better rules?

Posted by Simon Favre

Simon Favre In my previous post about TSMC making some DFM analysis steps mandatory at 45nm, I ended with a question about why the foundries can't just write better design rules (and rule decks) to make sure all designs yield well. This is a topic that has been discussed elsewhere, but here's my take on it. If we take a step back for a moment, there is something generic about DFM analysis that needs to be considered. … Read More

DRC, 45nm

1 Jun, 2009

John Ferguson I admit it.  I’m one of those rare adults who is actually willing to admit that he (or she) is a true fan of professional wrestling; have been since I was a kid in the early 70’s.  Over the entire course of those years, probably the greatest athlete in professional wrestling has been the recently retired  “Nature Boy” Ric Flair.  A multi-time world champ, one of Ric’s most prominent quotes has been … Read More

DRC, LVS, Physical Verification, Ric Flair

15 May, 2009

Are Design Rules Broken?

Posted by David Abercrombie

David Abercrombie

It is no mystery that the number of design rules has exploded over the past few technology nodes. It’s impossible for any human designer to “remember” them all, much less follow them all. It’s also a problem for the CAD engineer. We extracted some data from a spectrum of DRC decks that our customers have in production and the graph below shows the results. DRC Rule Count and Complexity by Technology

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Physical Verification, Design Rules, DRC, Design Rule Checking

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