Posted Mar 30, 2010, by Michael White
In both my last post, and in John Ferguson’s posts, the reasons, challenges and costs associated with “waivers” for DRC were discussed. As we have both pointed out, this is a growing problem as the IC industry increases its use of 3rd party IP while simultaneously the number of waivers within that IP is also increasing – resulting in a sea of waivers to deal with.
As we have deployed our Calibre … Read More
Tags:
Waiver,
Fab-lite,
Fabless,
Calibre,
IC Design,
Physical Verification,
Foundries,
Foundry
Posted Jan 28, 2010, by Michael White
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
Tags:
IDM,
IC Design,
Pattern Matching,
EDA,
SoC,
eqDRC,
Calibre,
Fabless,
Physical Verification,
Productivity,
Foundries,
Equation-Based DRC,
PV,
Sign-off,
Fab-lite
Posted Jan 15, 2010, by Michael White
Historically, design rule checking (DRC) was a black or white proposition—either you passed all your DRC’s or you fixed the errors until you did pass. Fast forward to today where much/most of the IP you use is from 3rd parties and/or your product has an increasing percentage of memory content and your design is never DRC clean at tape out. Your design team is now constantly waiving over and over and … Read More
Tags:
Foundry,
Foundries,
IC Design,
DRC,
SVRF,
EDA,
Tax,
Waiver,
Calibre,
Physical Verification,
Fab-lite,
Productivity,
Fabless,
Sign-off,
eqDRC,
SoC,
Equation-Based DRC
Posted Dec 17, 2009, by Michael White
Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers.
Why Do Competing PV Products Want to Use Calibre SVRF?
Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More
Tags:
Foundries,
Fabless,
Foundry,
TVF,
Translators,
Direct Read,
PV,
DRC,
Sign-off,
SVRF,
Calibre,
Syntax,
IC Design,
Equation-Based DRC,
IDM,
Fab-lite,
Native Read,
EDA,
Physical Verification,
eqDRC
Posted Nov 20, 2009, by David Abercrombie
In case you missed the webinar by Jim Culp on November 3rd, I wanted to give you an opportunity to see what you missed. Jim is a Senior Engineer in IBM’s Advanced Physical Design and Technology Integration team. He is leading a team in the development of Parametric DFM and the mitigation of Circuit Limited Yield (CLY). During the webinar he discussed how CLY is becoming the leading contributor to yield … Read More
Tags:
Power,
Physical Verification,
Yield,
Design Quality,
Design for Manufacturing,
IC Verification,
Leakage,
DRC,
IC Design
Posted Aug 20, 2009, by David Abercrombie
I got some questions from my last installment of this series asking for some pictures of defects that caused yield issues in production that could have been avoided during design. It struck me that most designers probably never get a chance to see the manufacturing problems their designs encounter. Since my background is in the fab, I wrongly assumed everyone had lived through the same pain as myself. … Read More
Tags:
Reliability,
IC Verification,
Yield,
Design Quality,
Design for Manufacturing,
Scoring,
Design Rules,
IC Design,
Physical Verification,
Design Rule Checking
Posted Aug 4, 2009, by David Abercrombie
I felt privileged this year to get a paper accepted into the technical track at DAC. It seems more and more difficult to get something through. I think they said they only had a 20% acceptance rate this year. I was glad to get to present this one because it was fun doing the experimentation for it and I think it helps answer one of the nagging questions I always get about eqDRC. I worked with Fedor … Read More
Tags:
IC Verification,
IC Design,
DAC,
Design Quality,
Design for Manufacturing,
Design Rules,
DRC,
Physical Verification,
Design Rule Checking
Posted Jul 31, 2009, by David Abercrombie
Well, day two of DAC started a little earlier than the first day. I had to attend the speakers breakfast for the paper I was going to give later that day. However, after breakfast I had my 9am suite presentation on eqDRC again and I also had a special guest again. This time it was Robert Boone from Freescale in Austin, TX. He works in the DFM team and he also agreed to come tell everyone what he and … Read More
Tags:
Reliability,
IC Verification,
Yield,
Physical Verification,
Design for Manufacturing,
DAC,
DRC,
IC Design,
Improvability,
Design Rule Checking,
Design Rules
Posted Jul 28, 2009, by David Abercrombie
Well it felt familiar to be back in San Francisco for DAC this year. However, I wasn’t ready for the cold. It was 100 degrees in Portland when I left and I always assume the Bay area will be warmer. Luckily I looked at the weather map before I finished packing and replaced my short sleeve shirts with long sleeve ones. I didn’t get in until late Sunday night so I only had time for a dinner in the Westin … Read More
Tags:
IC Verification,
IC Design,
Yield,
Design Quality,
Design for Manufacturing,
DAC,
Design Rules,
Leakage,
DRC,
Physical Verification,
Power,
Design Rule Checking
Posted Jul 2, 2009, by David Abercrombie
That is the question!
If you read my colleague John’s most recent posting “Waive of the future?”, you will understand the question. I was equally shocked as John to find that almost no one tapes out DRC clean anymore. I would add one other reason to John’s list as to why this has happened. I think the traditional DRC rules are broken. Please read my first post “Are Design Rules Broken?” for my stance … Read More
Tags:
IC Verification,
IC Design,
Design Quality,
Design for Manufacturing,
Design Rules,
DRC,
Physical Verification,
Design Rule Checking
