Posted Jan 28, 2010, by Michael White
Design rule checking (DRC) or physical verification used to be easy. For example, run some 1-D width and spacing checks to ensure things will resolve and won’t short and you are good to go. These checks were simple to write, fast to run and understandable, and quick to debug. Today is a new world order, where none of these attributes are true anymore. An increasing number of checks are 2-D, very … Read More
Tags:
IDM,
IC Design,
Pattern Matching,
EDA,
SoC,
eqDRC,
Calibre,
Fabless,
Physical Verification,
Productivity,
Foundries,
Equation-Based DRC,
PV,
Sign-off,
Fab-lite
Posted Dec 17, 2009, by Michael White
Since DAC we have heard a lot about physical verification tools claiming they can read the Calibre(R) SVRF/TVF syntax natively. This blog explores why competitive EDA companies are trying to use Calibre SVRF/TVF, the challenges involved, and the risks to customers.
Why Do Competing PV Products Want to Use Calibre SVRF?
Calibre is a primary sign-off standard at all the major foundries and IDMs, and … Read More
Tags:
Foundries,
Fabless,
Foundry,
TVF,
Translators,
Direct Read,
PV,
DRC,
Sign-off,
SVRF,
Calibre,
Syntax,
IC Design,
Equation-Based DRC,
IDM,
Fab-lite,
Native Read,
EDA,
Physical Verification,
eqDRC
