Designers are discovering a new class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must. There errors require electrical rule checking to complement the tradition layout checks.
Electrical rules are relatively complex, non-standard, and growing in number and type, creating a … Read More
IC Design Blog
Posts tagged with 'Low Power'
Clock designers are an enigma. Clock designers in general are die hard star wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in peak summer and have likeminded clock designers as best lunch buddies. Clock designers are notorious for making other lesser designers cry with their fancy PLL spice runs, non-negotiable … Read More
After some cautious and tentative moments, I finally managed to get my first post out. In this debut blog post, I’d like to introduce myself, present my bona fides and give you some idea about the likely content you’ll see here on a regular basis.
I’m Arvind Narayanan, Product Marketing Manager in the Place and Route Division at Mentor. I started my career as a Microprocessor design engineer for … Read More
Recent Posts
- Battle of Fins and BOXes
- TSMC 28nm yield (SemiWiki)
- DAC 2011 is upon us!
- Mentor Graphics User to User (U2U)
- Gate Oxide Breakdown Failures Highlight Industry Need for New Electrical Rule Checking Tools
- Dawn at the OASIS
- Layout Density and the Analog Cell
- Effects of Inception
- On-line session covering the DAC presentation for Calibre xACT 3D
- You can't give stuff away fast enough